79 lines
1.5 KiB
ArmAsm
79 lines
1.5 KiB
ArmAsm
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/* $Id: dec_and_lock.S,v 1.5 2001/11/18 00:12:56 davem Exp $
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* dec_and_lock.S: Sparc64 version of "atomic_dec_and_lock()"
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* using cas and ldstub instructions.
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*
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* Copyright (C) 2000 David S. Miller (davem@redhat.com)
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*/
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#include <linux/config.h>
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#include <asm/thread_info.h>
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.text
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.align 64
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/* CAS basically works like this:
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*
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* void CAS(MEM, REG1, REG2)
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* {
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* START_ATOMIC();
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* if (*(MEM) == REG1) {
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* TMP = *(MEM);
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* *(MEM) = REG2;
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* REG2 = TMP;
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* } else
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* REG2 = *(MEM);
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* END_ATOMIC();
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* }
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*/
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.globl _atomic_dec_and_lock
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_atomic_dec_and_lock: /* %o0 = counter, %o1 = lock */
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loop1: lduw [%o0], %g2
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subcc %g2, 1, %g7
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be,pn %icc, start_to_zero
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nop
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nzero: cas [%o0], %g2, %g7
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cmp %g2, %g7
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bne,pn %icc, loop1
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mov 0, %g1
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out:
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membar #StoreLoad | #StoreStore
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retl
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mov %g1, %o0
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start_to_zero:
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#ifdef CONFIG_PREEMPT
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ldsw [%g6 + TI_PRE_COUNT], %g3
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add %g3, 1, %g3
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stw %g3, [%g6 + TI_PRE_COUNT]
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#endif
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to_zero:
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ldstub [%o1], %g3
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brnz,pn %g3, spin_on_lock
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membar #StoreLoad | #StoreStore
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loop2: cas [%o0], %g2, %g7 /* ASSERT(g7 == 0) */
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cmp %g2, %g7
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be,pt %icc, out
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mov 1, %g1
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lduw [%o0], %g2
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subcc %g2, 1, %g7
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be,pn %icc, loop2
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nop
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membar #StoreStore | #LoadStore
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stb %g0, [%o1]
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#ifdef CONFIG_PREEMPT
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ldsw [%g6 + TI_PRE_COUNT], %g3
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sub %g3, 1, %g3
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stw %g3, [%g6 + TI_PRE_COUNT]
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#endif
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b,pt %xcc, nzero
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nop
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spin_on_lock:
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ldub [%o1], %g3
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brnz,pt %g3, spin_on_lock
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membar #LoadLoad
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ba,pt %xcc, to_zero
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nop
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nop
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