87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
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/*
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* intel_mid_dma.h - Intel MID DMA Drivers
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*
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* Copyright (C) 2008-10 Intel Corp
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* Author: Vinod Koul <vinod.koul@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*
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*/
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#ifndef __INTEL_MID_DMA_H__
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#define __INTEL_MID_DMA_H__
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#include <linux/dmaengine.h>
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/*DMA transaction width, src and dstn width would be same
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The DMA length must be width aligned,
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for 32 bit width the length must be 32 bit (4bytes) aligned only*/
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enum intel_mid_dma_width {
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LNW_DMA_WIDTH_8BIT = 0x0,
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LNW_DMA_WIDTH_16BIT = 0x1,
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LNW_DMA_WIDTH_32BIT = 0x2,
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};
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/*DMA mode configurations*/
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enum intel_mid_dma_mode {
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LNW_DMA_PER_TO_MEM = 0, /*periphral to memory configuration*/
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LNW_DMA_MEM_TO_PER, /*memory to periphral configuration*/
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LNW_DMA_MEM_TO_MEM, /*mem to mem confg (testing only)*/
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};
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/*DMA handshaking*/
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enum intel_mid_dma_hs_mode {
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LNW_DMA_HW_HS = 0, /*HW Handshaking only*/
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LNW_DMA_SW_HS = 1, /*SW Handshaking not recommended*/
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};
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/*Burst size configuration*/
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enum intel_mid_dma_msize {
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LNW_DMA_MSIZE_1 = 0x0,
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LNW_DMA_MSIZE_4 = 0x1,
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LNW_DMA_MSIZE_8 = 0x2,
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LNW_DMA_MSIZE_16 = 0x3,
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LNW_DMA_MSIZE_32 = 0x4,
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LNW_DMA_MSIZE_64 = 0x5,
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};
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/**
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* struct intel_mid_dma_slave - DMA slave structure
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*
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* @dirn: DMA trf direction
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* @src_width: tx register width
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* @dst_width: rx register width
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* @hs_mode: HW/SW handshaking mode
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* @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem)
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* @src_msize: Source DMA burst size
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* @dst_msize: Dst DMA burst size
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* @device_instance: DMA peripheral device instance, we can have multiple
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* peripheral device connected to single DMAC
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*/
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struct intel_mid_dma_slave {
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enum dma_data_direction dirn;
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enum intel_mid_dma_width src_width; /*width of DMA src txn*/
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enum intel_mid_dma_width dst_width; /*width of DMA dst txn*/
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enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/
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enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
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enum intel_mid_dma_msize src_msize; /*size if src burst*/
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enum intel_mid_dma_msize dst_msize; /*size of dst burst*/
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unsigned int device_instance; /*0, 1 for periphral instance*/
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};
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#endif /*__INTEL_MID_DMA_H__*/
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