44 lines
2.1 KiB
C
44 lines
2.1 KiB
C
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#ifndef _INCLUDE_SHANNON_H
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#define _INCLUDE_SHANNON_H
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/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT,
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* written by <forsyth@vitanuova.com> */
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#define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */
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#define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */
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/* lcd lower = GPIO 2-9 */
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#define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */
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#define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */
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#define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */
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#define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */
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#define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */
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#define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14
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#define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */
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#define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */
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#define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16
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#define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */
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#define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */
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#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
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#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
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#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
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#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
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/* XXX GPIO 23 unaccounted for */
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#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */
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#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24
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#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */
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#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25
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#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
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#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
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#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
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#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
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/* MCP UCB codec GPIO pins... */
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#define SHANNON_UCB_GPIO_BACKLIGHT 9
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#define SHANNON_UCB_GPIO_BRIGHT_MASK 7
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#define SHANNON_UCB_GPIO_BRIGHT 6
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#define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f
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#define SHANNON_UCB_GPIO_CONTRAST 0
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#endif
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