66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
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#ifndef BPA_IOMMU_H
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#define BPA_IOMMU_H
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/* some constants */
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enum {
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/* segment table entries */
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IOST_VALID_MASK = 0x8000000000000000ul,
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IOST_TAG_MASK = 0x3000000000000000ul,
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IOST_PT_BASE_MASK = 0x000003fffffff000ul,
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IOST_NNPT_MASK = 0x0000000000000fe0ul,
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IOST_PS_MASK = 0x000000000000000ful,
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IOST_PS_4K = 0x1,
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IOST_PS_64K = 0x3,
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IOST_PS_1M = 0x5,
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IOST_PS_16M = 0x7,
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/* iopt tag register */
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IOPT_VALID_MASK = 0x0000000200000000ul,
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IOPT_TAG_MASK = 0x00000001fffffffful,
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/* iopt cache register */
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IOPT_PROT_MASK = 0xc000000000000000ul,
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IOPT_PROT_NONE = 0x0000000000000000ul,
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IOPT_PROT_READ = 0x4000000000000000ul,
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IOPT_PROT_WRITE = 0x8000000000000000ul,
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IOPT_PROT_RW = 0xc000000000000000ul,
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IOPT_COHERENT = 0x2000000000000000ul,
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IOPT_ORDER_MASK = 0x1800000000000000ul,
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/* order access to same IOID/VC on same address */
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IOPT_ORDER_ADDR = 0x0800000000000000ul,
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/* similar, but only after a write access */
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IOPT_ORDER_WRITES = 0x1000000000000000ul,
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/* Order all accesses to same IOID/VC */
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IOPT_ORDER_VC = 0x1800000000000000ul,
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IOPT_RPN_MASK = 0x000003fffffff000ul,
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IOPT_HINT_MASK = 0x0000000000000800ul,
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IOPT_IOID_MASK = 0x00000000000007fful,
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IOSTO_ENABLE = 0x8000000000000000ul,
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IOSTO_ORIGIN = 0x000003fffffff000ul,
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IOSTO_HW = 0x0000000000000800ul,
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IOSTO_SW = 0x0000000000000400ul,
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IOCMD_CONF_TE = 0x0000800000000000ul,
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/* memory mapped registers */
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IOC_PT_CACHE_DIR = 0x000,
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IOC_ST_CACHE_DIR = 0x800,
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IOC_PT_CACHE_REG = 0x910,
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IOC_ST_ORIGIN = 0x918,
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IOC_CONF = 0x930,
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/* The high bit needs to be set on every DMA address,
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only 2GB are addressable */
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BPA_DMA_VALID = 0x80000000,
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BPA_DMA_MASK = 0x7fffffff,
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};
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void bpa_init_iommu(void);
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#endif
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