154 lines
4.3 KiB
ArmAsm
154 lines
4.3 KiB
ArmAsm
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Interrupt exception dispatch code.
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*
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*/
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#include <linux/config.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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/* A lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop and moving across
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* all the pending IRQ bits in the cause register is _NOT_ the answer, the
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* common case is one pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register IRQ mask, that
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* would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
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* between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the MIPS board look basically (barring software
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* IRQs which we don't use at all and all external interrupt sources are
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* combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* Note: On the SEAD board thing are a little bit different.
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* Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
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* wired to UART1.
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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.text
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.set noreorder
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.set noat
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.align 5
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NESTED(mipsIRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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mfc0 s0, CP0_CAUSE # get irq bits
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mfc0 s1, CP0_STATUS # get irq mask
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and s0, s1
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/* First we check for r4k counter/timer IRQ. */
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andi a0, s0, CAUSEF_IP7
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beq a0, zero, 1f
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andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
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/* Wheee, a timer interrupt. */
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move a0, sp
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jal mips_timer_interrupt
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nop
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j ret_from_irq
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nop
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1:
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#if defined(CONFIG_MIPS_SEAD)
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beq a0, zero, 1f
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andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
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#else
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beq a0, zero, 1f # delay slot, check hw3 interrupt
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andi a0, s0, CAUSEF_IP5
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#endif
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/* Wheee, combined hardware level zero interrupt. */
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#if defined(CONFIG_MIPS_ATLAS)
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jal atlas_hw0_irqdispatch
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#elif defined(CONFIG_MIPS_MALTA)
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jal malta_hw0_irqdispatch
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#elif defined(CONFIG_MIPS_SEAD)
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jal sead_hw0_irqdispatch
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#else
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#error "MIPS board not supported\n"
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#endif
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move a0, sp # delay slot
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j ret_from_irq
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nop # delay slot
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1:
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#if defined(CONFIG_MIPS_SEAD)
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beq a0, zero, 1f
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andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
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jal sead_hw1_irqdispatch
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move a0, sp # delay slot
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j ret_from_irq
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nop # delay slot
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1:
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#endif
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#if defined(CONFIG_MIPS_MALTA)
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beq a0, zero, 1f # check hw3 (coreHI) interrupt
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nop
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jal corehi_irqdispatch
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move a0, sp
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j ret_from_irq
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nop
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1:
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#endif
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/*
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* Here by mistake? This is possible, what can happen is that by the
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* time we take the exception the IRQ pin goes low, so just leave if
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* this is the case.
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*/
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move a1,s0
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PRINT("Got interrupt: c0_cause = %08x\n")
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mfc0 a1, CP0_EPC
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PRINT("c0_epc = %08x\n")
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j ret_from_irq
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nop
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END(mipsIRQ)
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