2005-04-17 06:20:36 +08:00
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/*
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2006-10-04 05:01:26 +08:00
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* arch/ppc/platforms/4xx/xparameters/xparameters.h
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2005-04-17 06:20:36 +08:00
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*
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2006-01-19 16:12:48 +08:00
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* This file includes the correct xparameters.h for the CONFIG'ed board plus
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* fixups to translate board specific XPAR values to a common set of names
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2005-04-17 06:20:36 +08:00
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
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* of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#if defined(CONFIG_XILINX_ML300)
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2006-01-19 16:12:48 +08:00
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#include "xparameters_ml300.h"
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2007-12-07 03:16:44 +08:00
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#define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
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XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
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#define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
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XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
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2006-01-19 16:13:37 +08:00
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#elif defined(CONFIG_XILINX_ML403)
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#include "xparameters_ml403.h"
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2007-12-07 03:16:44 +08:00
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#define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
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XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
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#define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
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XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
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2006-01-19 16:12:48 +08:00
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#else
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/* Add other board xparameter includes here before the #else */
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#error No xparameters_*.h file included
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#endif
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#ifndef SERIAL_PORT_DFNS
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/* zImage serial port definitions */
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#define RS_TABLE_SIZE 1
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#define SERIAL_PORT_DFNS { \
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.baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
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.irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
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.flags = ASYNC_BOOT_AUTOCONF, \
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.iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
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.iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM, \
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},
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2005-04-17 06:20:36 +08:00
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#endif
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2007-04-28 03:50:04 +08:00
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/*
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* A few reasonable defaults for the #defines which could be missing depending
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* on the IP version or variant (e.g. OPB vs PLB)
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*/
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#ifndef XPAR_EMAC_0_CAM_EXIST
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#define XPAR_EMAC_0_CAM_EXIST 0
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#endif
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#ifndef XPAR_EMAC_0_JUMBO_EXIST
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#define XPAR_EMAC_0_JUMBO_EXIST 0
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#endif
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#ifndef XPAR_EMAC_0_TX_DRE_TYPE
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#define XPAR_EMAC_0_TX_DRE_TYPE 0
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#endif
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#ifndef XPAR_EMAC_0_RX_DRE_TYPE
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#define XPAR_EMAC_0_RX_DRE_TYPE 0
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#endif
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#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
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#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
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#endif
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#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
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#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
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#endif
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#ifndef XPAR_EMAC_1_CAM_EXIST
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#define XPAR_EMAC_1_CAM_EXIST 0
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#endif
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#ifndef XPAR_EMAC_1_JUMBO_EXIST
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#define XPAR_EMAC_1_JUMBO_EXIST 0
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#endif
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#ifndef XPAR_EMAC_1_TX_DRE_TYPE
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#define XPAR_EMAC_1_TX_DRE_TYPE 0
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#endif
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#ifndef XPAR_EMAC_1_RX_DRE_TYPE
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#define XPAR_EMAC_1_RX_DRE_TYPE 0
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#endif
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#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
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#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
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#endif
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#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
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#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
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#endif
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#ifndef XPAR_GPIO_0_IS_DUAL
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#define XPAR_GPIO_0_IS_DUAL 0
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#endif
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#ifndef XPAR_GPIO_1_IS_DUAL
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#define XPAR_GPIO_1_IS_DUAL 0
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#endif
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#ifndef XPAR_GPIO_2_IS_DUAL
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#define XPAR_GPIO_2_IS_DUAL 0
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#endif
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#ifndef XPAR_GPIO_3_IS_DUAL
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#define XPAR_GPIO_3_IS_DUAL 0
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#endif
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#ifndef XPAR_GPIO_4_IS_DUAL
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#define XPAR_GPIO_4_IS_DUAL 0
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#endif
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