2005-04-17 06:20:36 +08:00
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/* Defines for using and allocating dma channels. */
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#ifndef _ASM_ARCH_DMA_H
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#define _ASM_ARCH_DMA_H
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#define MAX_DMA_CHANNELS 10
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/* dma0 and dma1 used for network (ethernet) */
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#define NETWORK_TX_DMA_NBR 0
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#define NETWORK_RX_DMA_NBR 1
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/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
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#define PAR0_TX_DMA_NBR 2
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#define PAR0_RX_DMA_NBR 3
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#define SCSI0_TX_DMA_NBR 2
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#define SCSI0_RX_DMA_NBR 3
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#define SER2_TX_DMA_NBR 2
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#define SER2_RX_DMA_NBR 3
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#define ATA_TX_DMA_NBR 2
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#define ATA_RX_DMA_NBR 3
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/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
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#define PAR1_TX_DMA_NBR 4
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#define PAR1_RX_DMA_NBR 5
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#define SCSI1_TX_DMA_NBR 4
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#define SCSI1_RX_DMA_NBR 5
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#define SER3_TX_DMA_NBR 4
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#define SER3_RX_DMA_NBR 5
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#define EXTDMA0_TX_DMA_NBR 4
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#define EXTDMA0_RX_DMA_NBR 5
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/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
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#define SER0_TX_DMA_NBR 6
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#define SER0_RX_DMA_NBR 7
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#define EXTDMA1_TX_DMA_NBR 6
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#define EXTDMA1_RX_DMA_NBR 7
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#define MEM2MEM_TX_DMA_NBR 6
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#define MEM2MEM_RX_DMA_NBR 7
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/* dma8 and dma9 shared by ser1 and usb */
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#define SER1_TX_DMA_NBR 8
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#define SER1_RX_DMA_NBR 9
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#define USB_TX_DMA_NBR 8
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#define USB_RX_DMA_NBR 9
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#endif
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2005-07-28 02:44:35 +08:00
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enum dma_owner
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{
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dma_eth,
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dma_ser0,
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dma_ser1, /* Async and sync */
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dma_ser2,
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dma_ser3, /* Async and sync */
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dma_ata,
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dma_par0,
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dma_par1,
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dma_ext0,
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dma_ext1,
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dma_int6,
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dma_int7,
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dma_usb,
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dma_scsi0,
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dma_scsi1
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};
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/* Masks used by cris_request_dma options: */
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#define DMA_VERBOSE_ON_ERROR (1<<0)
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#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
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int cris_request_dma(unsigned int dmanr, const char * device_id,
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unsigned options, enum dma_owner owner);
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void cris_free_dma(unsigned int dmanr, const char * device_id);
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