75 lines
2.5 KiB
ArmAsm
75 lines
2.5 KiB
ArmAsm
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/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* Based on arch/mips/tsdb/kernel/int-handler.S
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/jmr3927/jmr3927.h>
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/* A lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop
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* and moving across all the pending IRQ bits in the cause
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* register is _NOT_ the answer, the common case is one
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* pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register
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* IRQ mask, that would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs
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* off, nothing in between like BSD spl() brain-damage.
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*
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*/
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/* Flush write buffer (needed?)
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* NOTE: TX39xx performs "non-blocking load", so explicitly use the target
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* register of LBU to flush immediately.
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*/
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#define FLUSH_WB(tmp) \
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la tmp, JMR3927_IOC_REV_ADDR; \
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lbu tmp, (tmp); \
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move tmp, zero;
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.text
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.set noreorder
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.set noat
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.align 5
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NESTED(jmr3927_IRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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jal jmr3927_irc_irqdispatch
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move a0, sp
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FLUSH_WB(t0)
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j ret_from_irq
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nop
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END(jmr3927_IRQ)
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