OpenSDV
/
linux-stable-rt
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
linux-stable-rt/arch/blackfin/mach-bf561/Kconfig

223 lines
4.4 KiB
Plaintext
Raw Normal View History

blackfin architecture This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
if BF561
menu "BF561 Specific Configuration"
comment "Core B Support"
menu "Core B Support"
config BF561_COREB
bool "Enable Core B support"
default y
config BF561_COREB_RESET
bool "Enable Core B reset support"
default n
help
This requires code in the application that is loaded
into Core B. In order to reset, the application needs
to install an interrupt handler for Supplemental
Interrupt 0, that sets RETI to 0xff600000 and writes
bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
This causes Core B to stall when Supplemental Interrupt
0 is set, and will reset PC to 0xff600000 when
COREB_SRAM_INIT is cleared.
endmenu
comment "Interrupt Priority Assignment"
menu "Priority"
config IRQ_PLL_WAKEUP
int "PLL Wakeup Interrupt"
default 7
config IRQ_DMA1_ERROR
int "DMA1 Error (generic)"
default 7
config IRQ_DMA2_ERROR
int "DMA2 Error (generic)"
default 7
config IRQ_IMDMA_ERROR
int "IMDMA Error (generic)"
default 7
config IRQ_PPI0_ERROR
int "PPI0 Error Interrupt"
default 7
config IRQ_PPI1_ERROR
int "PPI1 Error Interrupt"
default 7
config IRQ_SPORT0_ERROR
int "SPORT0 Error Interrupt"
default 7
config IRQ_SPORT1_ERROR
int "SPORT1 Error Interrupt"
default 7
config IRQ_SPI_ERROR
int "SPI Error Interrupt"
default 7
config IRQ_UART_ERROR
int "UART Error Interrupt"
default 7
config IRQ_RESERVED_ERROR
int "Reserved Interrupt"
default 7
config IRQ_DMA1_0
int "DMA1 0 Interrupt(PPI1)"
default 8
config IRQ_DMA1_1
int "DMA1 1 Interrupt(PPI2)"
default 8
config IRQ_DMA1_2
int "DMA1 2 Interrupt"
default 8
config IRQ_DMA1_3
int "DMA1 3 Interrupt"
default 8
config IRQ_DMA1_4
int "DMA1 4 Interrupt"
default 8
config IRQ_DMA1_5
int "DMA1 5 Interrupt"
default 8
config IRQ_DMA1_6
int "DMA1 6 Interrupt"
default 8
config IRQ_DMA1_7
int "DMA1 7 Interrupt"
default 8
config IRQ_DMA1_8
int "DMA1 8 Interrupt"
default 8
config IRQ_DMA1_9
int "DMA1 9 Interrupt"
default 8
config IRQ_DMA1_10
int "DMA1 10 Interrupt"
default 8
config IRQ_DMA1_11
int "DMA1 11 Interrupt"
default 8
config IRQ_DMA2_0
int "DMA2 0 (SPORT0 RX)"
default 9
config IRQ_DMA2_1
int "DMA2 1 (SPORT0 TX)"
default 9
config IRQ_DMA2_2
int "DMA2 2 (SPORT1 RX)"
default 9
config IRQ_DMA2_3
int "DMA2 3 (SPORT2 TX)"
default 9
config IRQ_DMA2_4
int "DMA2 4 (SPI)"
default 9
config IRQ_DMA2_5
int "DMA2 5 (UART RX)"
default 9
config IRQ_DMA2_6
int "DMA2 6 (UART TX)"
default 9
config IRQ_DMA2_7
int "DMA2 7 Interrupt"
default 9
config IRQ_DMA2_8
int "DMA2 8 Interrupt"
default 9
config IRQ_DMA2_9
int "DMA2 9 Interrupt"
default 9
config IRQ_DMA2_10
int "DMA2 10 Interrupt"
default 9
config IRQ_DMA2_11
int "DMA2 11 Interrupt"
default 9
config IRQ_TIMER0
int "TIMER 0 Interrupt"
default 10
config IRQ_TIMER1
int "TIMER 1 Interrupt"
default 10
config IRQ_TIMER2
int "TIMER 2 Interrupt"
default 10
config IRQ_TIMER3
int "TIMER 3 Interrupt"
default 10
config IRQ_TIMER4
int "TIMER 4 Interrupt"
default 10
config IRQ_TIMER5
int "TIMER 5 Interrupt"
default 10
config IRQ_TIMER6
int "TIMER 6 Interrupt"
default 10
config IRQ_TIMER7
int "TIMER 7 Interrupt"
default 10
config IRQ_TIMER8
int "TIMER 8 Interrupt"
default 10
config IRQ_TIMER9
int "TIMER 9 Interrupt"
default 10
config IRQ_TIMER10
int "TIMER 10 Interrupt"
default 10
config IRQ_TIMER11
int "TIMER 11 Interrupt"
default 10
config IRQ_PROG0_INTA
int "Programmable Flags0 A (8)"
default 11
config IRQ_PROG0_INTB
int "Programmable Flags0 B (8)"
default 11
config IRQ_PROG1_INTA
int "Programmable Flags1 A (8)"
default 11
config IRQ_PROG1_INTB
int "Programmable Flags1 B (8)"
default 11
config IRQ_PROG2_INTA
int "Programmable Flags2 A (8)"
default 11
config IRQ_PROG2_INTB
int "Programmable Flags2 B (8)"
default 11
config IRQ_DMA1_WRRD0
int "MDMA1 0 write/read INT"
default 8
config IRQ_DMA1_WRRD1
int "MDMA1 1 write/read INT"
default 8
config IRQ_DMA2_WRRD0
int "MDMA2 0 write/read INT"
default 9
config IRQ_DMA2_WRRD1
int "MDMA2 1 write/read INT"
default 9
config IRQ_IMDMA_WRRD0
int "IMDMA 0 write/read INT"
default 12
config IRQ_IMDMA_WRRD1
int "IMDMA 1 write/read INT"
default 12
config IRQ_WDTIMER
int "Watch Dog Timer"
default 13
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif