2008-03-18 16:02:50 +08:00
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#ifndef ____ASM_ARCH_SDRC_H
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#define ____ASM_ARCH_SDRC_H
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/*
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* OMAP2/3 SDRC/SMS register definitions
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2008-08-05 23:14:15 +08:00
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#include <mach/io.h>
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2008-03-18 16:02:50 +08:00
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/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
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#define SDRC_SYSCONFIG 0x010
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#define SDRC_DLLA_CTRL 0x060
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#define SDRC_DLLA_STATUS 0x064
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#define SDRC_DLLB_CTRL 0x068
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#define SDRC_DLLB_STATUS 0x06C
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#define SDRC_POWER 0x070
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#define SDRC_MR_0 0x084
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#define SDRC_RFR_CTRL_0 0x0a4
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/*
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* These values represent the number of memory clock cycles between
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* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
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* rows per device, and include a subtraction of a 50 cycle window in the
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* event that the autorefresh command is delayed due to other SDRC activity.
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* The '| 1' sets the ARE field to send one autorefresh when the autorefresh
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* counter reaches 0.
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*
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* These represent optimal values for common parts, it won't work for all.
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* As long as you scale down, most parameters are still work, they just
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* become sub-optimal. The RFR value goes in the opposite direction. If you
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* don't adjust it down as your clock period increases the refresh interval
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* will not be met. Setting all parameters for complete worst case may work,
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* but may cut memory performance by 2x. Due to errata the DLLs need to be
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* unlocked and their value needs run time calibration. A dynamic call is
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* need for that as no single right value exists acorss production samples.
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*
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* Only the FULL speed values are given. Current code is such that rate
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* changes must be made at DPLLoutx2. The actual value adjustment for low
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* frequency operation will be handled by omap_set_performance()
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*
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* By having the boot loader boot up in the fastest L4 speed available likely
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* will result in something which you can switch between.
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*/
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#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
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#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
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#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
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#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
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#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
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/*
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* SMS register access
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*/
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#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
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#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
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#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
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/* SMS register offsets - read/write with sms_{read,write}_reg() */
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#define SMS_SYSCONFIG 0x010
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/* REVISIT: fill in other SMS registers here */
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#endif
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