56 lines
1.5 KiB
ArmAsm
56 lines
1.5 KiB
ArmAsm
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/*
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* arch/arm/mach-spear6xx/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for SPEAr6xx machine family
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*
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* Copyright (C) 2009 ST Microelectronics
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* Rajeev Kumar<rajeev-dlh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/spear.h>
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#include <asm/hardware/vic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
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ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
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mov \irqnr, #0
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teq \irqstat, #0
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bne 1001f
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ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
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ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
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teq \irqstat, #0
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beq 1002f @ this will set/reset
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@ zero register
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mov \irqnr, #32
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1001:
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/*
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* Following code will find bit position of least significang
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* bit set in irqstat, using following equation
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* least significant bit set in n = (n & ~(n-1))
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*/
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sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
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mvn \tmp, \tmp @ tmp = ~tmp
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and \irqstat, \irqstat, \tmp @ irqstat &= tmp
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/* Now, irqstat is = bit no. of 1st bit set in vic irq status */
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clz \tmp, \irqstat @ tmp = leading zeros
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rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1
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add \irqnr, \irqnr, \tmp
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1002: /* EQ will be set if no irqs pending */
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.endm
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