2005-04-17 06:20:36 +08:00
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/* system.h: FR-V CPU control definitions
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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2007-06-06 17:39:40 +08:00
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#include <linux/types.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/linkage.h>
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2008-02-09 07:00:45 +08:00
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#include <linux/kernel.h>
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2005-04-17 06:20:36 +08:00
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struct thread_struct;
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'.
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* The `mb' is to tell GCC not to cache `current' across this call.
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*/
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extern asmlinkage
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struct task_struct *__switch_to(struct thread_struct *prev_thread,
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struct thread_struct *next_thread,
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struct task_struct *prev);
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#define switch_to(prev, next, last) \
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do { \
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(prev)->thread.sched_lr = \
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(unsigned long) __builtin_return_address(0); \
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(last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
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mb(); \
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} while(0)
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/*
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* interrupt flag manipulation
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[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
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* - use virtual interrupt management since touching the PSR is slow
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* - ICC2.Z: T if interrupts virtually disabled
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* - ICC2.C: F if interrupts really disabled
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* - if Z==1 upon interrupt:
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* - C is set to 0
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* - interrupts are really disabled
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* - entry.S returns immediately
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* - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
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* - if taken, the trap:
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* - sets ICC2.C
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* - enables interrupts
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2005-04-17 06:20:36 +08:00
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*/
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[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
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#define local_irq_disable() \
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do { \
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/* set Z flag, but don't change the C flag */ \
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asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_irq_enable() \
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do { \
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/* clear Z flag and then test the C flag */ \
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asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
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" tihi icc2,gr0,#2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_save_flags(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm volatile("movsg ccr,%0" \
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: "=r"(flags) \
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: \
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: "memory"); \
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\
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/* shift ICC2.Z to bit 0 */ \
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flags >>= 26; \
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\
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/* make flags 1 if interrupts disabled, 0 otherwise */ \
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flags &= 1UL; \
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} while(0)
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#define irqs_disabled() \
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2008-07-13 04:47:58 +08:00
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({unsigned long flags; local_save_flags(flags); !!flags; })
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[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
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#define local_irq_save(flags) \
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do { \
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typecheck(unsigned long, flags); \
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local_save_flags(flags); \
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local_irq_disable(); \
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} while(0)
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#define local_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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\
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/* load the Z flag by turning 1 if disabled into 0 if disabled \
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* and thus setting the Z flag but not the C flag */ \
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asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
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/* then test Z=0 and C=0 */ \
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" tihi icc2,gr0,#2 \n" \
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: \
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: "r"(flags) \
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: "memory", "icc2" \
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); \
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\
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} while(0)
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/*
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* real interrupt flag manipulation
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*/
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#define __local_irq_disable() \
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2005-04-17 06:20:36 +08:00
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%2,%0 \n" \
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" ori %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
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#define __local_irq_enable() \
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2005-04-17 06:20:36 +08:00
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
|
|
|
#define __local_save_flags(flags) \
|
2005-04-17 06:20:36 +08:00
|
|
|
do { \
|
|
|
|
|
typecheck(unsigned long, flags); \
|
|
|
|
|
asm("movsg psr,%0" \
|
|
|
|
|
: "=r"(flags) \
|
|
|
|
|
: \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
|
|
|
#define __local_irq_save(flags) \
|
2005-04-17 06:20:36 +08:00
|
|
|
do { \
|
|
|
|
|
unsigned long npsr; \
|
|
|
|
|
typecheck(unsigned long, flags); \
|
|
|
|
|
asm volatile(" movsg psr,%0 \n" \
|
|
|
|
|
" andi %0,%3,%1 \n" \
|
|
|
|
|
" ori %1,%2,%1 \n" \
|
|
|
|
|
" movgs %1,psr \n" \
|
|
|
|
|
: "=r"(flags), "=r"(npsr) \
|
|
|
|
|
: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
|
|
|
#define __local_irq_restore(flags) \
|
2005-04-17 06:20:36 +08:00
|
|
|
do { \
|
|
|
|
|
typecheck(unsigned long, flags); \
|
|
|
|
|
asm volatile(" movgs %0,psr \n" \
|
|
|
|
|
: \
|
|
|
|
|
: "r" (flags) \
|
|
|
|
|
: "memory"); \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the
processor status register (PSR) are relatively slow and because we will
soon have the need to deal with multiple interrupt controls at the same
time (separate h/w and inter-core interrupts).
The way this is done is to dedicate one of the four integer condition code
registers (ICC2) to maintaining a virtual interrupt disablement state
whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate
whether the interrupts are virtually disabled and the ICC2.C flag (Carry)
to indicate whether the interrupts are physically disabled.
ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set
to indicate interrupts are physically enabled. Under normal running
conditions Z==0 and C==1.
Disabling interrupts with local_irq_disable() doesn't then actually
physically disable interrupts - it merely sets ICC2.Z to 1. Should an
interrupt then happen, the exception prologue will note ICC2.Z is set and
branch out of line using one instruction (an unlikely BEQ). Here it will
physically disable interrupts and clear ICC2.C.
When it comes time to enable interrupts (local_irq_enable()), this simply
clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are
clear (the HI integer condition). This can be done with the TIHI
conditional trap instruction.
The trap then physically reenables interrupts and sets ICC2.C again. Upon
returning the interrupt will be taken as interrupts will then be enabled.
Note that whilst processing the trap, the whole exceptions system is
disabled, and so an interrupt can't happen till it returns.
If no pending interrupt had happened, ICC2.C would still be set, the HI
condition would not be fulfilled, and no trap will happen.
Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z
flag out of the CCR register, shifting it down and masking it off. This
gives a result of 0 if interrupts were enabled and 1 if they weren't.
Restoring interrupts (local_irq_restore) is then a matter of taking the
saved value mentioned previously and XOR'ing it against 1. If it was one,
the result will be zero, and if it was zero the result will be non-zero.
This result is then used to affect the ICC2.Z flag directly (it is a
condition code flag after all). An XOR instruction does not affect the
Carry flag, and so that bit of state is unchanged. The two flags can then
be sampled to see if they're both zero using the trap (TIHI) as for the
unconditional reenablement (local_irq_enable).
This patch also:
(1) Modifies the debugging stub (break.S) to handle single-stepping crossing
into the trap #2 handler and into virtually disabled interrupts.
(2) Removes superseded fixup pointers from the second instructions in the trap
tables (there's no a separate fixup table for this).
(3) Declares the trap #3 vector for use in .org directives in the trap table.
(4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with
virtual interrupt handling, and removes the duplicate code that has now
been folded into irq_exit() (softirq and preemption handling).
(5) Tells the compiler in the arch Makefile that ICC2 is now reserved.
(6) Documents the in-kernel ABI, including the virtual interrupts.
(7) Renames the old irq management functions to different names.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 05:53:20 +08:00
|
|
|
#define __irqs_disabled() \
|
2005-04-17 06:20:36 +08:00
|
|
|
((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Force strict CPU ordering.
|
|
|
|
|
*/
|
|
|
|
|
#define nop() asm volatile ("nop"::)
|
|
|
|
|
#define mb() asm volatile ("membar" : : :"memory")
|
|
|
|
|
#define rmb() asm volatile ("membar" : : :"memory")
|
|
|
|
|
#define wmb() asm volatile ("membar" : : :"memory")
|
2008-05-14 12:35:11 +08:00
|
|
|
#define read_barrier_depends() do { } while (0)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-04-10 23:11:05 +08:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
#define smp_mb() mb()
|
|
|
|
|
#define smp_rmb() rmb()
|
|
|
|
|
#define smp_wmb() wmb()
|
2005-04-17 06:20:36 +08:00
|
|
|
#define smp_read_barrier_depends() read_barrier_depends()
|
2008-04-10 23:11:05 +08:00
|
|
|
#define set_mb(var, value) \
|
|
|
|
|
do { xchg(&var, (value)); } while (0)
|
|
|
|
|
#else
|
|
|
|
|
#define smp_mb() barrier()
|
|
|
|
|
#define smp_rmb() barrier()
|
|
|
|
|
#define smp_wmb() barrier()
|
|
|
|
|
#define smp_read_barrier_depends() do {} while(0)
|
|
|
|
|
#define set_mb(var, value) \
|
|
|
|
|
do { var = (value); barrier(); } while (0)
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
|
|
|
|
|
extern void free_initmem(void);
|
|
|
|
|
|
|
|
|
|
#define arch_align_stack(x) (x)
|
|
|
|
|
|
2007-05-08 15:34:38 +08:00
|
|
|
/*****************************************************************************/
|
|
|
|
|
/*
|
|
|
|
|
* compare and conditionally exchange value with memory
|
|
|
|
|
* - if (*ptr == test) then orig = *ptr; *ptr = test;
|
|
|
|
|
* - if (*ptr != test) then orig = *ptr;
|
|
|
|
|
*/
|
FRV: Implement atomic64_t
Implement atomic64_t and its ops for FRV. Tested with the following patch:
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index 55e4fab..086d50d 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -746,6 +746,52 @@ static void __init parse_cmdline_early(char *cmdline)
} /* end parse_cmdline_early() */
+static atomic64_t xxx;
+
+static void test_atomic64(void)
+{
+ atomic64_set(&xxx, 0x12300000023LL);
+
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0x12300000023LL);
+ mb();
+ if (atomic64_inc_return(&xxx) != 0x12300000024LL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0x12300000024LL);
+ mb();
+ if (atomic64_sub_return(0x36900000050LL, &xxx) != -0x2460000002cLL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != -0x2460000002cLL);
+ mb();
+ if (atomic64_dec_return(&xxx) != -0x2460000002dLL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != -0x2460000002dLL);
+ mb();
+ if (atomic64_add_return(0x36800000001LL, &xxx) != 0x121ffffffd4LL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL);
+ mb();
+ if (atomic64_cmpxchg(&xxx, 0x123456789abcdefLL, 0x121ffffffd4LL) != 0x121ffffffd4LL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL);
+ mb();
+ if (atomic64_cmpxchg(&xxx, 0x121ffffffd4LL, 0x123456789abcdefLL) != 0x121ffffffd4LL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0x123456789abcdefLL);
+ mb();
+ if (atomic64_xchg(&xxx, 0xabcdef123456789LL) != 0x123456789abcdefLL)
+ BUG();
+ mb();
+ BUG_ON(atomic64_read(&xxx) != 0xabcdef123456789LL);
+ mb();
+}
+
/*****************************************************************************/
/*
*
@@ -845,6 +891,8 @@ void __init setup_arch(char **cmdline_p)
// asm volatile("movgs %0,timerd" :: "r"(10000000));
// __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
+ test_atomic64();
+
} /* end setup_arch() */
#if 0
Note that this doesn't cover all the trivial wrappers, but does cover all the
substantial implementations.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-02 07:46:16 +08:00
|
|
|
extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v);
|
|
|
|
|
|
2007-05-08 15:34:38 +08:00
|
|
|
#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
|
|
|
|
|
|
|
|
|
|
#define cmpxchg(ptr, test, new) \
|
|
|
|
|
({ \
|
|
|
|
|
__typeof__(ptr) __xg_ptr = (ptr); \
|
|
|
|
|
__typeof__(*(ptr)) __xg_orig, __xg_tmp; \
|
|
|
|
|
__typeof__(*(ptr)) __xg_test = (test); \
|
|
|
|
|
__typeof__(*(ptr)) __xg_new = (new); \
|
|
|
|
|
\
|
|
|
|
|
switch (sizeof(__xg_orig)) { \
|
|
|
|
|
case 4: \
|
|
|
|
|
asm volatile( \
|
|
|
|
|
"0: \n" \
|
|
|
|
|
" orcc gr0,gr0,gr0,icc3 \n" \
|
|
|
|
|
" ckeq icc3,cc7 \n" \
|
|
|
|
|
" ld.p %M0,%1 \n" \
|
|
|
|
|
" orcr cc7,cc7,cc3 \n" \
|
|
|
|
|
" sub%I4cc %1,%4,%2,icc0 \n" \
|
|
|
|
|
" bne icc0,#0,1f \n" \
|
|
|
|
|
" cst.p %3,%M0 ,cc3,#1 \n" \
|
|
|
|
|
" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
|
|
|
|
|
" beq icc3,#0,0b \n" \
|
|
|
|
|
"1: \n" \
|
|
|
|
|
: "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
|
|
|
|
|
: "r"(__xg_new), "NPr"(__xg_test) \
|
|
|
|
|
: "memory", "cc7", "cc3", "icc3", "icc0" \
|
|
|
|
|
); \
|
|
|
|
|
break; \
|
|
|
|
|
\
|
|
|
|
|
default: \
|
2008-03-29 11:08:18 +08:00
|
|
|
__xg_orig = (__typeof__(__xg_orig))0; \
|
2007-05-08 15:34:38 +08:00
|
|
|
asm volatile("break"); \
|
|
|
|
|
break; \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
__xg_orig; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
|
|
|
|
|
|
|
|
|
|
#define cmpxchg(ptr, test, new) \
|
|
|
|
|
({ \
|
|
|
|
|
__typeof__(ptr) __xg_ptr = (ptr); \
|
|
|
|
|
__typeof__(*(ptr)) __xg_orig; \
|
|
|
|
|
__typeof__(*(ptr)) __xg_test = (test); \
|
|
|
|
|
__typeof__(*(ptr)) __xg_new = (new); \
|
|
|
|
|
\
|
|
|
|
|
switch (sizeof(__xg_orig)) { \
|
2007-10-15 02:35:10 +08:00
|
|
|
case 4: __xg_orig = (__force __typeof__(*ptr)) \
|
|
|
|
|
__cmpxchg_32((__force uint32_t *)__xg_ptr, \
|
|
|
|
|
(__force uint32_t)__xg_test, \
|
|
|
|
|
(__force uint32_t)__xg_new); break; \
|
2007-05-08 15:34:38 +08:00
|
|
|
default: \
|
2008-03-29 11:08:18 +08:00
|
|
|
__xg_orig = (__typeof__(__xg_orig))0; \
|
2007-05-08 15:34:38 +08:00
|
|
|
asm volatile("break"); \
|
|
|
|
|
break; \
|
|
|
|
|
} \
|
|
|
|
|
\
|
|
|
|
|
__xg_orig; \
|
|
|
|
|
})
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-02-07 16:16:14 +08:00
|
|
|
#include <asm-generic/cmpxchg-local.h>
|
|
|
|
|
|
|
|
|
|
static inline unsigned long __cmpxchg_local(volatile void *ptr,
|
|
|
|
|
unsigned long old,
|
|
|
|
|
unsigned long new, int size)
|
|
|
|
|
{
|
|
|
|
|
switch (size) {
|
|
|
|
|
case 4:
|
2008-02-09 07:00:45 +08:00
|
|
|
return cmpxchg((unsigned long *)ptr, old, new);
|
2008-02-07 16:16:14 +08:00
|
|
|
default:
|
|
|
|
|
return __cmpxchg_local_generic(ptr, old, new, size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return old;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
|
|
|
|
|
* them available.
|
|
|
|
|
*/
|
|
|
|
|
#define cmpxchg_local(ptr, o, n) \
|
|
|
|
|
((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
|
|
|
|
|
(unsigned long)(n), sizeof(*(ptr))))
|
|
|
|
|
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
2007-05-08 15:34:38 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif /* _ASM_SYSTEM_H */
|
