250 lines
8.2 KiB
C
250 lines
8.2 KiB
C
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#ifndef __iop_timer_grp_defs_h
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#define __iop_timer_grp_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/io_proc/rtl/iop_timer_grp.r
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* id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
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* last modfied: Mon Apr 11 16:08:46 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
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* id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope iop_timer_grp */
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/* Register rw_cfg, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int clk_src : 1;
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unsigned int trig : 2;
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unsigned int clk_gen_div : 8;
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unsigned int clk_div : 8;
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unsigned int dummy1 : 13;
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} reg_iop_timer_grp_rw_cfg;
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#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
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#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
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/* Register rw_half_period, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int quota_lo : 15;
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unsigned int quota_hi : 15;
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unsigned int quota_hi_sel : 1;
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unsigned int dummy1 : 1;
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} reg_iop_timer_grp_rw_half_period;
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#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
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#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
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/* Register rw_half_period_len, scope iop_timer_grp, type rw */
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typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
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#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
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#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
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#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
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/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int clk_src : 3;
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unsigned int strb : 2;
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unsigned int run_mode : 2;
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unsigned int out_mode : 1;
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unsigned int active_on_tmr : 2;
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unsigned int inv : 1;
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unsigned int en_by_tmr : 2;
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unsigned int dis_by_tmr : 2;
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unsigned int en_only_by_reg : 1;
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unsigned int dis_only_by_reg : 1;
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unsigned int rst_at_en_strb : 1;
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unsigned int dummy1 : 14;
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} reg_iop_timer_grp_rw_tmr_cfg;
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#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
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#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
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#define STRIDE_iop_timer_grp_rw_tmr_len 4
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/* Register rw_tmr_len, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int val : 16;
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unsigned int dummy1 : 16;
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} reg_iop_timer_grp_rw_tmr_len;
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#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
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#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
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/* Register rw_cmd, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int rst : 4;
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unsigned int en : 4;
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unsigned int dis : 4;
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unsigned int strb : 4;
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unsigned int dummy1 : 16;
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} reg_iop_timer_grp_rw_cmd;
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#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
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#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
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/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
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typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
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#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
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#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
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/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
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typedef struct {
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unsigned int val : 16;
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unsigned int dummy1 : 16;
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} reg_iop_timer_grp_rs_tmr_cnt;
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#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
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#define STRIDE_iop_timer_grp_r_tmr_cnt 8
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/* Register r_tmr_cnt, scope iop_timer_grp, type r */
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typedef struct {
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unsigned int val : 16;
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unsigned int dummy1 : 16;
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} reg_iop_timer_grp_r_tmr_cnt;
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#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
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/* Register rw_intr_mask, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int tmr2 : 1;
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unsigned int tmr3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_timer_grp_rw_intr_mask;
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#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
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#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
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/* Register rw_ack_intr, scope iop_timer_grp, type rw */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int tmr2 : 1;
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unsigned int tmr3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_timer_grp_rw_ack_intr;
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#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
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#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
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/* Register r_intr, scope iop_timer_grp, type r */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int tmr2 : 1;
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unsigned int tmr3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_timer_grp_r_intr;
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#define REG_RD_ADDR_iop_timer_grp_r_intr 108
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/* Register r_masked_intr, scope iop_timer_grp, type r */
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typedef struct {
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unsigned int tmr0 : 1;
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unsigned int tmr1 : 1;
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unsigned int tmr2 : 1;
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unsigned int tmr3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_timer_grp_r_masked_intr;
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#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
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/* Constants */
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enum {
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regk_iop_timer_grp_clk200 = 0x00000000,
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regk_iop_timer_grp_clk_gen = 0x00000002,
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regk_iop_timer_grp_complete = 0x00000002,
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regk_iop_timer_grp_div_clk200 = 0x00000001,
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regk_iop_timer_grp_div_clk_gen = 0x00000003,
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regk_iop_timer_grp_ext = 0x00000001,
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regk_iop_timer_grp_hi = 0x00000000,
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regk_iop_timer_grp_long_period = 0x00000001,
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regk_iop_timer_grp_neg = 0x00000002,
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regk_iop_timer_grp_no = 0x00000000,
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regk_iop_timer_grp_once = 0x00000003,
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regk_iop_timer_grp_pause = 0x00000001,
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regk_iop_timer_grp_pos = 0x00000001,
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regk_iop_timer_grp_pos_neg = 0x00000003,
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regk_iop_timer_grp_pulse = 0x00000000,
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regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004,
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regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004,
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regk_iop_timer_grp_rw_cfg_default = 0x00000002,
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regk_iop_timer_grp_rw_intr_mask_default = 0x00000000,
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regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000,
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regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900,
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regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200,
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regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00,
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regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004,
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regk_iop_timer_grp_rw_tmr_len_default = 0x00000000,
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regk_iop_timer_grp_rw_tmr_len_size = 0x00000004,
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regk_iop_timer_grp_short_period = 0x00000000,
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regk_iop_timer_grp_stop = 0x00000000,
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regk_iop_timer_grp_tmr = 0x00000004,
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regk_iop_timer_grp_toggle = 0x00000001,
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regk_iop_timer_grp_yes = 0x00000001
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};
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#endif /* __iop_timer_grp_defs_h */
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