2005-04-17 06:20:36 +08:00
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/*
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* Hardware info about DECstation DS2100/3100 systems (otherwise known as
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* pmin/pmax or KN01).
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
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* are by courtesy of Chris Fraser.
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2005-06-23 04:56:26 +08:00
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
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2005-04-17 06:20:36 +08:00
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*/
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#ifndef __ASM_MIPS_DEC_KN01_H
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#define __ASM_MIPS_DEC_KN01_H
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#include <asm/addrspace.h>
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2005-06-17 04:30:54 +08:00
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#define KN01_SLOT_BASE CKSEG1ADDR(0x10000000)
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2005-04-17 06:20:36 +08:00
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#define KN01_SLOT_SIZE 0x01000000
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/*
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* Address ranges for devices.
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*/
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#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
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#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
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#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
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#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
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#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
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#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
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#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
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#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
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#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
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#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
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#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
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#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
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#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
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#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
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#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
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#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
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#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
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/*
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* Some port addresses...
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*/
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#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
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#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
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#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
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/*
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* Frame buffer memory address.
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*/
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2005-06-17 04:30:54 +08:00
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#define KN01_VFB_MEM CKSEG1ADDR(0x0fc00000)
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2005-04-17 06:20:36 +08:00
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/*
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* CPU interrupt bits.
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*/
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#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
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#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
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#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
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#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
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#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
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#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
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/*
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* System Control & Status Register bits.
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*/
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#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
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#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
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#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
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#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
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#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
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#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
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#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
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#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
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#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
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#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
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#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
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#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
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2005-06-23 04:56:26 +08:00
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#ifndef __ASSEMBLY__
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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struct pt_regs;
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extern u16 cached_kn01_csr;
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extern spinlock_t kn01_lock;
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extern void dec_kn01_be_init(void);
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extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
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extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
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struct pt_regs *regs);
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#endif
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2005-04-17 06:20:36 +08:00
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#endif /* __ASM_MIPS_DEC_KN01_H */
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