2010-04-01 19:30:19 +08:00
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/*
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* arch/arm/mach-spear3xx/include/mach/spear320.h
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*
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* SPEAr320 Machine specific definition
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifdef CONFIG_MACH_SPEAR320
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#ifndef __MACH_SPEAR320_H
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#define __MACH_SPEAR320_H
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2011-03-07 12:57:08 +08:00
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#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
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#define SPEAR320_FSMC_BASE UL(0x4C000000)
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#define SPEAR320_NAND_BASE UL(0x50000000)
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#define SPEAR320_I2S_BASE UL(0x60000000)
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#define SPEAR320_SDHCI_BASE UL(0x70000000)
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#define SPEAR320_CLCD_BASE UL(0x90000000)
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#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
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#define SPEAR320_CAN0_BASE UL(0xA1000000)
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#define SPEAR320_CAN1_BASE UL(0xA2000000)
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#define SPEAR320_UART1_BASE UL(0xA3000000)
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#define SPEAR320_UART2_BASE UL(0xA4000000)
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#define SPEAR320_SSP0_BASE UL(0xA5000000)
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#define SPEAR320_SSP1_BASE UL(0xA6000000)
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#define SPEAR320_I2C_BASE UL(0xA7000000)
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#define SPEAR320_PWM_BASE UL(0xA8000000)
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#define SPEAR320_SMII0_BASE UL(0xAA000000)
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#define SPEAR320_SMII1_BASE UL(0xAB000000)
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#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
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2011-03-07 12:57:07 +08:00
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2010-05-03 16:24:30 +08:00
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/* Interrupt registers offsets and masks */
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2011-05-20 15:34:21 +08:00
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#define SPEAR320_INT_STS_MASK_REG 0x04
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#define SPEAR320_INT_CLR_MASK_REG 0x04
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#define SPEAR320_INT_ENB_MASK_REG 0x08
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#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
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#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
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#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
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#define SPEAR320_EMI_IRQ_MASK (1 << 7)
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#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
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#define SPEAR320_SPP_IRQ_MASK (1 << 9)
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#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
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#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
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#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
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#define SPEAR320_UART1_IRQ_MASK (1 << 13)
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#define SPEAR320_UART2_IRQ_MASK (1 << 14)
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#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
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#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
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#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
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#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
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#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
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#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
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#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
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2010-05-03 16:24:30 +08:00
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2011-05-20 15:34:21 +08:00
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#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
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#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
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#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
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2010-04-01 19:30:19 +08:00
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#endif /* __MACH_SPEAR320_H */
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#endif /* CONFIG_MACH_SPEAR320 */
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