2009-01-07 23:14:38 +08:00
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/* mach/dma.h - arch-specific DMA defines
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2008-11-18 17:48:22 +08:00
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*
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2009-01-07 23:14:38 +08:00
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* Copyright 2004-2008 Analog Devices Inc.
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2008-11-18 17:48:22 +08:00
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*
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2009-01-07 23:14:38 +08:00
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* Licensed under the GPL-2 or later.
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2008-11-18 17:48:22 +08:00
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define CH_PPI 0
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#define CH_SPORT0_RX 1
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#define CH_SPORT0_TX 2
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#define CH_SPORT1_RX 3
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#define CH_SPORT1_TX 4
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#define CH_SPI0 5
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#define CH_UART0_RX 6
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#define CH_UART0_TX 7
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#define CH_SPORT2_RX 8
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#define CH_SPORT2_TX 9
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#define CH_SPORT3_RX 10
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#define CH_SPORT3_TX 11
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#define CH_SPI1 14
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#define CH_SPI2 15
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#define CH_UART1_RX 16
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#define CH_UART1_TX 17
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#define CH_UART2_RX 18
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#define CH_UART2_TX 19
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#define CH_MEM_STREAM0_DEST 20
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#define CH_MEM_STREAM0_SRC 21
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#define CH_MEM_STREAM1_DEST 22
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#define CH_MEM_STREAM1_SRC 23
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#define CH_MEM_STREAM2_DEST 24
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#define CH_MEM_STREAM2_SRC 25
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#define CH_MEM_STREAM3_DEST 26
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#define CH_MEM_STREAM3_SRC 27
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2009-01-07 23:14:39 +08:00
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#define MAX_DMA_CHANNELS 28
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2008-11-18 17:48:22 +08:00
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#endif
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