2005-04-17 06:20:36 +08:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994-1996 Linus Torvalds & authors
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*
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* Copied from i386; many of the especially older MIPS or ISA-based platforms
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* are basically identical. Using this file probably implies i8259 PIC
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* support in a system but the very least interrupt numbers 0 - 15 need to
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* be put aside for legacy devices.
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*/
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#ifndef __ASM_MACH_GENERIC_IDE_H
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#define __ASM_MACH_GENERIC_IDE_H
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#ifdef __KERNEL__
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#include <linux/pci.h>
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#include <linux/stddef.h>
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2005-04-19 20:26:59 +08:00
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#include <asm/processor.h>
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2005-04-17 06:20:36 +08:00
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#ifndef MAX_HWIFS
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# ifdef CONFIG_BLK_DEV_IDEPCI
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#define MAX_HWIFS 10
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# else
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#define MAX_HWIFS 6
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# endif
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#endif
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#define IDE_ARCH_OBSOLETE_DEFAULTS
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2007-09-04 22:02:02 +08:00
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static __inline__ int ide_probe_legacy(void)
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{
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#ifdef CONFIG_PCI
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struct pci_dev *dev;
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/*
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* This can be called on the ide_setup() path, super-early in
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* boot. But the down_read() will enable local interrupts,
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* which can cause some machines to crash. So here we detect
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* and flag that situation and bail out early.
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*/
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if (no_pci_devices())
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return 0;
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dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
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if (dev)
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goto found;
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dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
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if (dev)
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goto found;
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return 0;
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found:
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pci_dev_put(dev);
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return 1;
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#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
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return 1;
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#else
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return 0;
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#endif
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}
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2005-04-17 06:20:36 +08:00
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static __inline__ int ide_default_irq(unsigned long base)
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{
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2007-08-08 00:18:28 +08:00
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switch (base) {
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case 0x1f0: return 14;
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case 0x170: return 15;
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case 0x1e8: return 11;
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case 0x168: return 10;
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case 0x1e0: return 8;
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case 0x160: return 12;
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2005-04-17 06:20:36 +08:00
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default:
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return 0;
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2007-08-08 00:18:28 +08:00
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}
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2005-04-17 06:20:36 +08:00
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}
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static __inline__ unsigned long ide_default_io_base(int index)
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{
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2007-09-04 22:02:02 +08:00
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if (!ide_probe_legacy())
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return 0;
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2007-08-08 00:18:28 +08:00
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/*
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* If PCI is present then it is not safe to poke around
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* the other legacy IDE ports. Only 0x1f0 and 0x170 are
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* defined compatibility mode ports for PCI. A user can
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* override this using ide= but we must default safe.
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*/
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if (no_pci_devices()) {
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2005-04-17 06:20:36 +08:00
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switch (index) {
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2007-08-08 00:18:28 +08:00
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case 2: return 0x1e8;
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case 3: return 0x168;
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case 4: return 0x1e0;
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case 5: return 0x160;
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2005-04-17 06:20:36 +08:00
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}
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2007-08-08 00:18:28 +08:00
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}
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switch (index) {
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case 0: return 0x1f0;
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case 1: return 0x170;
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default:
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2005-04-17 06:20:36 +08:00
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return 0;
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2007-08-08 00:18:28 +08:00
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}
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2005-04-17 06:20:36 +08:00
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}
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#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
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#ifdef CONFIG_BLK_DEV_IDEPCI
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#define ide_init_default_irq(base) (0)
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#else
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#define ide_init_default_irq(base) ide_default_irq(base)
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#endif
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/* MIPS port and memory-mapped I/O string operations. */
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2006-04-06 03:42:04 +08:00
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static inline void __ide_flush_prologue(void)
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{
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#ifdef CONFIG_SMP
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if (cpu_has_dc_aliases)
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preempt_disable();
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#endif
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}
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static inline void __ide_flush_epilogue(void)
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{
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#ifdef CONFIG_SMP
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if (cpu_has_dc_aliases)
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preempt_enable();
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#endif
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}
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2005-04-17 06:20:36 +08:00
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2005-04-19 20:26:59 +08:00
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static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
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{
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if (cpu_has_dc_aliases) {
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unsigned long end = addr + size;
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2006-04-06 03:42:04 +08:00
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while (addr < end) {
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local_flush_data_cache_page((void *)addr);
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addr += PAGE_SIZE;
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}
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2005-04-19 20:26:59 +08:00
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}
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}
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2006-04-06 03:42:04 +08:00
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/*
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* insw() and gang might be called with interrupts disabled, so we can't
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* send IPIs for flushing due to the potencial of deadlocks, see the comment
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* above smp_call_function() in arch/mips/kernel/smp.c. We work around the
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* problem by disabling preemption so we know we actually perform the flush
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* on the processor that actually has the lines to be flushed which hopefully
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* is even better for performance anyway.
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*/
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2005-04-19 20:26:59 +08:00
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static inline void __ide_insw(unsigned long port, void *addr,
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unsigned int count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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insw(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 2);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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insl(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 4);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_outsw(unsigned long port, const void *addr,
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unsigned long count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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outsw(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 2);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_outsl(unsigned long port, const void *addr,
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unsigned long count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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outsl(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 4);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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readsw(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 2);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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readsl(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 4);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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writesw(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 2);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
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{
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2006-04-06 03:42:04 +08:00
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__ide_flush_prologue();
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2005-04-19 20:26:59 +08:00
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writesl(port, addr, count);
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__ide_flush_dcache_range((unsigned long)addr, count * 4);
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2006-04-06 03:42:04 +08:00
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__ide_flush_epilogue();
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2005-04-19 20:26:59 +08:00
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}
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2005-04-17 06:20:36 +08:00
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2005-04-19 20:26:59 +08:00
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/* ide_insw calls insw, not __ide_insw. Why? */
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#undef insw
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#undef insl
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2005-11-06 22:58:21 +08:00
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#undef outsw
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#undef outsl
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2005-04-19 20:26:59 +08:00
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#define insw(port, addr, count) __ide_insw(port, addr, count)
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#define insl(port, addr, count) __ide_insl(port, addr, count)
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2005-11-06 22:58:21 +08:00
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#define outsw(port, addr, count) __ide_outsw(port, addr, count)
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#define outsl(port, addr, count) __ide_outsl(port, addr, count)
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2005-04-17 06:20:36 +08:00
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#endif /* __KERNEL__ */
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#endif /* __ASM_MACH_GENERIC_IDE_H */
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