2005-04-17 06:20:36 +08:00
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/*
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2008-08-02 17:55:55 +08:00
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* arch/arm/include/asm/map.h
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2005-04-17 06:20:36 +08:00
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*
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* Copyright (C) 1999-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Page table mapping constructs and function prototypes
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*/
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2007-05-06 03:59:27 +08:00
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#include <asm/io.h>
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2005-04-17 06:20:36 +08:00
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struct map_desc {
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unsigned long virtual;
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2005-10-28 22:19:11 +08:00
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unsigned long pfn;
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2005-04-17 06:20:36 +08:00
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unsigned long length;
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unsigned int type;
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};
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[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 20:17:11 +08:00
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/* types 0-4 are defined in asm/io.h */
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#define MT_CACHECLEAN 5
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#define MT_MINICLEAN 6
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#define MT_LOW_VECTORS 7
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#define MT_HIGH_VECTORS 8
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#define MT_MEMORY 9
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#define MT_ROM 10
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2007-05-06 03:28:16 +08:00
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#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
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#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
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2005-04-17 06:20:36 +08:00
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2006-06-25 00:34:50 +08:00
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#ifdef CONFIG_MMU
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2005-04-17 06:20:36 +08:00
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extern void iotable_init(struct map_desc *, int);
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2006-06-25 00:34:50 +08:00
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#else
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#define iotable_init(map,num) do { } while (0)
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#endif
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