279 lines
7.3 KiB
C
279 lines
7.3 KiB
C
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/*
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* linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
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*
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* May be copied or modified under the terms of the GNU General Public License
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*
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*
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* 00:12.0 Unknown mass storage controller:
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* Triones Technologies, Inc.
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* Unknown device 0003 (rev 01)
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*
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* hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
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* hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
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* hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
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* hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
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* hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
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* hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
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*
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* ide-pci.c reference
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*
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* Since there are two cards that report almost identically,
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* the only discernable difference is the values reported in pcicmd.
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* Booting-BIOS card or HPT363 :: pcicmd == 0x07
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* Non-bootable card or HPT343 :: pcicmd == 0x05
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#define HPT343_DEBUG_DRIVE_INFO 0
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static u8 hpt34x_ratemask (ide_drive_t *drive)
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{
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return 1;
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}
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static void hpt34x_clear_chipset (ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
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pci_read_config_dword(dev, 0x44, ®1);
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pci_read_config_dword(dev, 0x48, ®2);
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tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
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tmp2 = (reg2 & ~(0x11 << drive->dn));
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pci_write_config_dword(dev, 0x44, tmp1);
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pci_write_config_dword(dev, 0x48, tmp2);
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}
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static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
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u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
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u8 hi_speed, lo_speed;
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hi_speed = speed >> 4;
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lo_speed = speed & 0x0f;
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if (hi_speed & 7) {
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hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
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} else {
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lo_speed <<= 5;
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lo_speed >>= 5;
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}
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pci_read_config_dword(dev, 0x44, ®1);
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pci_read_config_dword(dev, 0x48, ®2);
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tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
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tmp2 = ((hi_speed << drive->dn) | reg2);
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pci_write_config_dword(dev, 0x44, tmp1);
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pci_write_config_dword(dev, 0x48, tmp2);
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#if HPT343_DEBUG_DRIVE_INFO
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printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
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" (0x%02x 0x%02x)\n",
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drive->name, ide_xfer_verbose(speed),
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drive->dn, reg1, tmp1, reg2, tmp2,
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hi_speed, lo_speed);
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#endif /* HPT343_DEBUG_DRIVE_INFO */
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return(ide_config_drive_speed(drive, speed));
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}
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static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
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{
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pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
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hpt34x_clear_chipset(drive);
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(void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
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}
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/*
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* This allows the configuration of ide_pci chipset registers
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* for cards that learn about the drive's UDMA, DMA, PIO capabilities
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* after the drive is reported by the OS. Initially for designed for
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* HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
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*/
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static int config_chipset_for_dma (ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
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if (!(speed))
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return 0;
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hpt34x_clear_chipset(drive);
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(void) hpt34x_tune_chipset(drive, speed);
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return ide_dma_enable(drive);
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}
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static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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drive->init_speed = 0;
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if (id && (id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (config_chipset_for_dma(drive))
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#ifndef CONFIG_HPT34X_AUTODMA
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return hwif->ide_dma_off_quietly(drive);
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#else
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return hwif->ide_dma_on(drive);
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#endif
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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hpt34x_tune_drive(drive, 255);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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/*
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* If the BIOS does not set the IO base addaress to XX00, 343 will fail.
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*/
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#define HPT34X_PCI_INIT_REG 0x80
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static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
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{
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int i = 0;
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unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
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unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
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unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
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u16 cmd;
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unsigned long flags;
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local_irq_save(flags);
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pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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if (cmd & PCI_COMMAND_MEMORY) {
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if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
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pci_write_config_byte(dev, PCI_ROM_ADDRESS,
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dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
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printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
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dev->resource[PCI_ROM_RESOURCE].start);
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}
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
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} else {
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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}
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/*
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* Since 20-23 can be assigned and are R/W, we correct them.
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*/
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pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
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for(i=0; i<4; i++) {
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dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
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dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
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dev->resource[i].flags = IORESOURCE_IO;
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pci_write_config_dword(dev,
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(PCI_BASE_ADDRESS_0 + (i * 4)),
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dev->resource[i].start);
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}
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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local_irq_restore(flags);
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return dev->irq;
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}
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static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
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{
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u16 pcicmd = 0;
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hwif->autodma = 0;
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hwif->tuneproc = &hpt34x_tune_drive;
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hwif->speedproc = &hpt34x_tune_chipset;
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hwif->no_dsc = 1;
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
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if (!hwif->dma_base)
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return;
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hwif->ultra_mask = 0x07;
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
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if (!noautodma)
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hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static ide_pci_device_t hpt34x_chipset __devinitdata = {
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.name = "HPT34X",
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.init_chipset = init_chipset_hpt34x,
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.init_hwif = init_hwif_hpt34x,
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.channels = 2,
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.autodma = NOAUTODMA,
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.bootable = NEVER_BOARD,
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.extra = 16
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};
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static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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ide_pci_device_t *d = &hpt34x_chipset;
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static char *chipset_names[] = {"HPT343", "HPT345"};
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u16 pcicmd = 0;
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pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
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d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
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d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
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return ide_setup_pci_device(dev, d);
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}
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static struct pci_device_id hpt34x_pci_tbl[] = {
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{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
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static struct pci_driver driver = {
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.name = "HPT34x_IDE",
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.id_table = hpt34x_pci_tbl,
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.probe = hpt34x_init_one,
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};
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static int hpt34x_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(hpt34x_ide_init);
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MODULE_AUTHOR("Andre Hedrick");
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MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
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MODULE_LICENSE("GPL");
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