2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Carsten Langgaard, carstenl@mips.com
|
|
|
|
|
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can distribute it and/or modify it
|
|
|
|
|
* under the terms of the GNU General Public License (Version 2) as
|
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
|
|
|
* for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License along
|
|
|
|
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
|
|
|
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
|
|
|
|
*
|
|
|
|
|
* Defines for the SEAD interrupt controller.
|
|
|
|
|
*/
|
|
|
|
|
#ifndef _MIPS_SEADINT_H
|
|
|
|
|
#define _MIPS_SEADINT_H
|
|
|
|
|
|
2005-11-16 00:10:01 +08:00
|
|
|
/*
|
|
|
|
|
* Interrupts 0..7 are used for SEAD CPU interrupts
|
|
|
|
|
*/
|
|
|
|
|
#define MIPSCPU_INT_BASE 0
|
|
|
|
|
|
|
|
|
|
#define MIPSCPU_INT_UART0 2
|
|
|
|
|
#define MIPSCPU_INT_UART1 3
|
|
|
|
|
|
|
|
|
|
#define MIPSCPU_INT_CPUCTR 7
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#endif /* !(_MIPS_SEADINT_H) */
|
