105 lines
2.6 KiB
ArmAsm
105 lines
2.6 KiB
ArmAsm
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/*
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* DDR SDRAM initialization - alter with care
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* This file is intended to be included from other assembler files
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*
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* Note: This file may not modify r8 or r9 because they are used to
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* carry information from the decompresser to the kernel
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*
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* Copyright (C) 2005-2007 Axis Communications AB
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*
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* Authors: Mikael Starvik <starvik@axis.com>
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*/
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/* Just to be certain the config file is included, we include it here
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* explicitely instead of depending on it being included in the file that
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* uses this code.
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*/
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#include <hwregs/asm/reg_map_asm.h>
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#include <hwregs/asm/ddr2_defs_asm.h>
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;; WARNING! The registers r8 and r9 are used as parameters carrying
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;; information from the decompressor (if the kernel was compressed).
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;; They should not be used in the code below.
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;; Refer to ddr2 MDS for initialization sequence
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; Start clock
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
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move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
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move.d $r1, [$r0]
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; Reset phy and start calibration
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
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move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
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REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
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move.d $r1, [$r0]
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move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
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move.d $r1, [$r0]
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; 2. Wait 200us
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move.d 10000, $r2
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1: bne 1b
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subq 1, $r2
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; Issue commands
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
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move.d sdram_commands_start, $r2
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command_loop:
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movu.b [$r2+], $r1
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movu.w [$r2+], $r3
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do_cmd:
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lslq 16, $r1
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or.d $r3, $r1
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move.d $r1, [$r0]
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cmp.d sdram_commands_end, $r2
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blo command_loop
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nop
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; Set timing
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
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move.d CONFIG_ETRAX_DDR2_TIMING, $r1
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move.d $r1, [$r0]
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; Set latency
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
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move.d 0x13, $r1
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move.d $r1, [$r0]
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; Set configuration
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
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move.d CONFIG_ETRAX_DDR2_CONFIG, $r1
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move.d $r1, [$r0]
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ba after_sdram_commands
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nop
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sdram_commands_start:
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.byte regk_ddr2_deselect
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.word 0
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.byte regk_ddr2_pre
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.word regk_ddr2_pre_all
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.byte regk_ddr2_emrs2
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.word 0
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.byte regk_ddr2_emrs3
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.word 0
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.byte regk_ddr2_emrs
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.word regk_ddr2_dll_en
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.byte regk_ddr2_mrs
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.word regk_ddr2_dll_rst
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.byte regk_ddr2_pre
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.word regk_ddr2_pre_all
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.byte regk_ddr2_ref
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.word 0
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.byte regk_ddr2_ref
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.word 0
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.byte regk_ddr2_mrs
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.word CONFIG_ETRAX_DDR2_MRS & 0xffff
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.byte regk_ddr2_emrs
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.word regk_ddr2_ocd_default | regk_ddr2_dll_en
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.byte regk_ddr2_emrs
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.word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
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sdram_commands_end:
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.align 1
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after_sdram_commands:
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