76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
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/*
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* Memory MAP
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* Common header file for blackfin BF561 of processors.
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*/
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#ifndef _MEM_MAP_561_H_
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#define _MEM_MAP_561_H_
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#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
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#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
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/* Async Memory Banks */
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#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
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#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
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#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
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#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
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#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
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/* Level 1 Memory */
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#ifdef CONFIG_BLKFIN_CACHE
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#define BLKFIN_ICACHESIZE (16*1024)
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#else
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#define BLKFIN_ICACHESIZE (0*1024)
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#endif
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/* Memory Map for ADSP-BF561 processors */
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#ifdef CONFIG_BF561
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#define L1_CODE_START 0xFFA00000
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#define L1_DATA_A_START 0xFF800000
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#define L1_DATA_B_START 0xFF900000
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#define L1_CODE_LENGTH 0x4000
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#ifdef CONFIG_BLKFIN_DCACHE
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#ifdef CONFIG_BLKFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BLKFIN_DCACHESIZE (16*1024)
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#define BLKFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BLKFIN_DCACHESIZE (32*1024)
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#define BLKFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BLKFIN_DCACHESIZE (0*1024)
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#define BLKFIN_DSUPBANKS 0
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#endif /*CONFIG_BLKFIN_DCACHE*/
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#endif
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/* Level 2 Memory */
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#define L2_START 0xFEB00000
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#define L2_LENGTH 0x20000
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/* Scratch Pad Memory */
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#if defined(CONFIG_BF561)
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#define L1_SCRATCH_START 0xFFB00000
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#define L1_SCRATCH_LENGTH 0x1000
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#endif
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#endif /* _MEM_MAP_533_H_ */
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