114 lines
6.3 KiB
C
114 lines
6.3 KiB
C
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/*
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* File: include/asm-blackfin/mach-bf518/defBF514.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _DEF_BF514_H
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#define _DEF_BF514_H
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/* Include all Core registers and bit definitions */
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#include <asm/def_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
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/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
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#include "defBF51x_base.h"
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/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
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/* SDH Registers */
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#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
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#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
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#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
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#define SDH_COMMAND 0xFFC0390C /* SDH Command */
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#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
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#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
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#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
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#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
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#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
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#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
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#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
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#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
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#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
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#define SDH_STATUS 0xFFC03934 /* SDH Status */
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#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
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#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
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#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
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#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
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#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
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#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
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#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
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#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
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#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
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#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
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#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
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#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
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#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
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#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
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#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
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#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
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#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
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/* Removable Storage Interface Registers */
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#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
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#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
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#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
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#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
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#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
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#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
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#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
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#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
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#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
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#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
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#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
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#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
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#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
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#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
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#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
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#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
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#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
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#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
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#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
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#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
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#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
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#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
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#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
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#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
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#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
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#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
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#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
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#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
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#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
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#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
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#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
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#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
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#endif /* _DEF_BF514_H */
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