130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
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/*
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* cbe_regs.h
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*
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* This file is intended to hold the various register definitions for CBE
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* on-chip system devices (memory controller, IO controller, etc...)
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*
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* (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*/
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#ifndef CBE_REGS_H
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#define CBE_REGS_H
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/*
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*
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* Some HID register definitions
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*
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*/
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/* CBE specific HID0 bits */
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#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
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#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
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#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
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#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
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/*
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*
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* Pervasive unit register definitions
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*
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*/
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struct cbe_pmd_regs {
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u8 pad_0x0000_0x0800[0x0800 - 0x0000]; /* 0x0000 */
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/* Thermal Sensor Registers */
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u64 ts_ctsr1; /* 0x0800 */
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u64 ts_ctsr2; /* 0x0808 */
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u64 ts_mtsr1; /* 0x0810 */
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u64 ts_mtsr2; /* 0x0818 */
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u64 ts_itr1; /* 0x0820 */
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u64 ts_itr2; /* 0x0828 */
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u64 ts_gitr; /* 0x0830 */
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u64 ts_isr; /* 0x0838 */
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u64 ts_imr; /* 0x0840 */
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u64 tm_cr1; /* 0x0848 */
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u64 tm_cr2; /* 0x0850 */
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u64 tm_simr; /* 0x0858 */
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u64 tm_tpr; /* 0x0860 */
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u64 tm_str1; /* 0x0868 */
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u64 tm_str2; /* 0x0870 */
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u64 tm_tsr; /* 0x0878 */
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/* Power Management */
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u64 pm_control; /* 0x0880 */
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#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
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u64 pm_status; /* 0x0888 */
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/* Time Base Register */
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u64 tbr; /* 0x0890 */
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u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
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/* Fault Isolation Registers */
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u64 checkstop_fir; /* 0x0c00 */
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u64 recoverable_fir;
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u64 spec_att_mchk_fir;
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u64 fir_mode_reg;
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u64 fir_enable_mask;
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u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */
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};
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extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
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extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
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/*
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*
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* IIC unit register definitions
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*
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*/
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struct cbe_iic_pending_bits {
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u32 data;
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u8 flags;
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u8 class;
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u8 source;
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u8 prio;
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};
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#define CBE_IIC_IRQ_VALID 0x80
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#define CBE_IIC_IRQ_IPI 0x40
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struct cbe_iic_thread_regs {
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struct cbe_iic_pending_bits pending;
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struct cbe_iic_pending_bits pending_destr;
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u64 generate;
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u64 prio;
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};
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struct cbe_iic_regs {
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u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
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/* IIC interrupt registers */
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struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
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u64 iic_ir; /* 0x0440 */
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u64 iic_is; /* 0x0448 */
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u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
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/* IOC FIR */
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u64 ioc_fir_reset; /* 0x0500 */
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u64 ioc_fir_set;
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u64 ioc_checkstop_enable;
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u64 ioc_fir_error_mask;
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u64 ioc_syserr_enable;
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u64 ioc_fir;
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u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
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};
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extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
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extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
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/* Init this module early */
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extern void cbe_regs_init(void);
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#endif /* CBE_REGS_H */
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