OpenSDV
/
linux-stable-rt
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap 

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (31 commits)
  ARM: OMAP: Fix export.h or module.h includes
  ARM: OMAP: omap_device: Include linux/export.h
  ARM: OMAP2: Fix H4 matrix keyboard warning
  ARM: OMAP1: Remove unused omap-alsa.h
  ARM: OMAP1: Fix warnings about enabling 32 KiHz timer
  ARM: OMAP2+: timer: Remove omap_device_pm_latency
  ARM: OMAP2+: clock data: Remove redundant timer clkdev
  ARM: OMAP: Devkit8000: Remove double omap_mux_init_gpio
  ARM: OMAP: usb: musb: OMAP: Delete unused function
  MAINTAINERS: Update linux-omap git repository
  ARM: OMAP: change get_context_loss_count ret value to int
  ARM: OMAP4: hsmmc: configure SDMMC1_DR0 properly
  ARM: OMAP4: hsmmc: Fix Pbias configuration on regulator OFF
  ARM: OMAP3: hwmod: fix variant registration and remove SmartReflex from common list
  ARM: OMAP: I2C: Fix omap_register_i2c_bus() return value on success
  ARM: OMAP: dmtimer: Include linux/module.h
  ARM: OMAP2+: l3-noc: Include linux/module.h
  ARM: OMAP2+: devices: Fixes for McPDM
  ARM: OMAP: Fix errors and warnings when building for one board
  ARM: OMAP3: PM: restrict erratum i443 handling to OMAP3430 only
  ...
This commit is contained in:
Linus Torvalds 2011-11-07 16:14:26 -08:00
parent a3fbbde70a d30cc16c8e
commit 075cb105cb
42 changed files with 344 additions and 401 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -4673,7 +4673,7 @@ L: linux-omap@vger.kernel.org
W: http://www.muru.com/linux/omap/
W: http://linux.omap.com/
Q: http://patchwork.kernel.org/project/linux-omap/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
S: Maintained
F: arch/arm/*omap*/

1
arch/arm/mach-omap1/board-palmz71.c
View File

@ -42,7 +42,6 @@
#include <plat/irda.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/omap-alsa.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>

2
arch/arm/mach-omap1/pm.c
View File

@ -116,7 +116,7 @@ void omap1_pm_idle(void)
return;
}
#ifdef CONFIG_OMAP_MPU_TIMER
#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
#warning Enable 32kHz OS timer in order to allow sleep states in idle
use_idlect1 = use_idlect1 & ~(1 << 9);
#else

1
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -226,7 +226,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
{
int ret;
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);

8
arch/arm/mach-omap2/board-generic.c
View File

@ -28,6 +28,7 @@
* XXX: Still needed to boot until the i2c & twl driver is adapted to
* device-tree
*/
#ifdef CONFIG_ARCH_OMAP4
static struct twl4030_platform_data sdp4430_twldata = {
.irq_base = TWL6030_IRQ_BASE,
.irq_end = TWL6030_IRQ_END,
@ -37,7 +38,9 @@ static void __init omap4_i2c_init(void)
{
omap4_pmic_init("twl6030", &sdp4430_twldata);
}
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct twl4030_platform_data beagle_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@ -47,6 +50,7 @@ static void __init omap3_i2c_init(void)
{
omap3_pmic_init("twl4030", &beagle_twldata);
}
#endif
static struct of_device_id omap_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
@ -72,17 +76,21 @@ static void __init omap_generic_init(void)
of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
}
#ifdef CONFIG_ARCH_OMAP4
static void __init omap4_init(void)
{
omap4_i2c_init();
omap_generic_init();
}
#endif
#ifdef CONFIG_ARCH_OMAP3
static void __init omap3_init(void)
{
omap3_i2c_init();
omap_generic_init();
}
#endif
#if defined(CONFIG_SOC_OMAP2420)
static const char *omap242x_boards_compat[] __initdata = {

122
arch/arm/mach-omap2/board-h4.c
View File

@ -25,6 +25,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/input/matrix_keypad.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -34,7 +35,6 @@
#include <plat/usb.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/keypad.h>
#include <plat/menelaus.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
@ -50,10 +50,8 @@
#define H4_ETHR_GPIO_IRQ 92
static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
static const unsigned int h4_keymap[] = {
#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
static const uint32_t board_matrix_keys[] = {
KEY(0, 0, KEY_LEFT),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_A),
@ -86,6 +84,71 @@ static const unsigned int h4_keymap[] = {
KEY(4, 5, KEY_ENTER),
};
static const struct matrix_keymap_data board_keymap_data = {
.keymap = board_matrix_keys,
.keymap_size = ARRAY_SIZE(board_matrix_keys),
};
static unsigned int board_keypad_row_gpios[] = {
88, 89, 124, 11, 6, 96
};
static unsigned int board_keypad_col_gpios[] = {
90, 91, 100, 36, 12, 97, 98
};
static struct matrix_keypad_platform_data board_keypad_platform_data = {
.keymap_data = &board_keymap_data,
.row_gpios = board_keypad_row_gpios,
.num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios),
.col_gpios = board_keypad_col_gpios,
.num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios),
.active_low = 1,
.debounce_ms = 20,
.col_scan_delay_us = 5,
};
static struct platform_device board_keyboard = {
.name = "matrix-keypad",
.id = -1,
.dev = {
.platform_data = &board_keypad_platform_data,
},
};
static void __init board_mkp_init(void)
{
omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
if (omap_has_menelaus()) {
omap_mux_init_signal("sdrc_a14.gpio0",
OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
omap_mux_init_signal("gpio_98", 0);
board_keypad_row_gpios[5] = 0;
board_keypad_col_gpios[2] = 15;
board_keypad_col_gpios[6] = 18;
} else {
omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("gpio_100", 0);
omap_mux_init_signal("gpio_98", 0);
}
omap_mux_init_signal("gpio_90", 0);
omap_mux_init_signal("gpio_91", 0);
omap_mux_init_signal("gpio_36", 0);
omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
omap_mux_init_signal("gpio_97", 0);
platform_device_register(&board_keyboard);
}
#else
static inline void board_mkp_init(void)
{
}
#endif
static struct mtd_partition h4_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
@ -137,31 +200,8 @@ static struct platform_device h4_flash_device = {
.resource = &h4_flash_resource,
};
static const struct matrix_keymap_data h4_keymap_data = {
.keymap = h4_keymap,
.keymap_size = ARRAY_SIZE(h4_keymap),
};
static struct omap_kp_platform_data h4_kp_data = {
.rows = 6,
.cols = 7,
.keymap_data = &h4_keymap_data,
.rep = true,
.row_gpios = row_gpios,
.col_gpios = col_gpios,
};
static struct platform_device h4_kp_device = {
.name = "omap-keypad",
.id = -1,
.dev = {
.platform_data = &h4_kp_data,
},
};
static struct platform_device *h4_devices[] __initdata = {
&h4_flash_device,
&h4_kp_device,
};
static struct panel_generic_dpi_data h4_panel_data = {
@ -336,31 +376,7 @@ static void __init omap_h4_init(void)
* if not needed.
*/
#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
if (omap_has_menelaus()) {
omap_mux_init_signal("sdrc_a14.gpio0",
OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
omap_mux_init_signal("gpio_98", 0);
row_gpios[5] = 0;
col_gpios[2] = 15;
col_gpios[6] = 18;
} else {
omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("gpio_100", 0);
omap_mux_init_signal("gpio_98", 0);
}
omap_mux_init_signal("gpio_90", 0);
omap_mux_init_signal("gpio_91", 0);
omap_mux_init_signal("gpio_36", 0);
omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
omap_mux_init_signal("gpio_97", 0);
#endif
board_mkp_init();
i2c_register_board_info(1, h4_i2c_board_info,
ARRAY_SIZE(h4_i2c_board_info));

51
arch/arm/mach-omap2/clkt_dpll.c
View File

@ -46,10 +46,19 @@
(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define DPLL_FINT_BAND1_MIN 750000
#define DPLL_FINT_BAND1_MAX 2100000
#define DPLL_FINT_BAND2_MIN 7500000
#define DPLL_FINT_BAND2_MAX 21000000
#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
/*
* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
* From device data manual section 4.3 "DPLL and DLL Specifications".
*/
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
#define OMAP3PLUS_DPLL_FINT_MIN 32000
#define OMAP3PLUS_DPLL_FINT_MAX 52000000
/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW -1
@ -71,33 +80,43 @@
static int _dpll_test_fint(struct clk *clk, u8 n)
{
struct dpll_data *dd;
long fint;
long fint, fint_min, fint_max;
int ret = 0;
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
fint = clk->parent->rate / n;
if (fint < DPLL_FINT_BAND1_MIN) {
if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */
WARN(1, "No fint limits available for OMAP2!\n");
return DPLL_FINT_INVALID;
} else if (cpu_is_omap3430()) {
fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
} else if (dd->flags & DPLL_J_TYPE) {
fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
} else {
fint_min = OMAP3PLUS_DPLL_FINT_MIN;
fint_max = OMAP3PLUS_DPLL_FINT_MAX;
}
if (fint < fint_min) {
pr_debug("rejecting n=%d due to Fint failure, "
"lowering max_divider\n", n);
dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW;
} else if (fint > DPLL_FINT_BAND1_MAX &&
fint < DPLL_FINT_BAND2_MIN) {
pr_debug("rejecting n=%d due to Fint failure\n", n);
ret = DPLL_FINT_INVALID;
} else if (fint > DPLL_FINT_BAND2_MAX) {
} else if (fint > fint_max) {
pr_debug("rejecting n=%d due to Fint failure, "
"boosting min_divider\n", n);
dd->min_divider = n;
ret = DPLL_FINT_INVALID;
} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
pr_debug("rejecting n=%d due to Fint failure\n", n);
ret = DPLL_FINT_INVALID;
}
return ret;

2
arch/arm/mach-omap2/clock.h
View File

@ -66,6 +66,8 @@ void omap3_noncore_dpll_disable(struct clk *clk);
int omap4_dpllmx_gatectrl_read(struct clk *clk);
void omap4_dpllmx_allow_gatectrl(struct clk *clk);
void omap4_dpllmx_deny_gatectrl(struct clk *clk);
long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);

12
arch/arm/mach-omap2/clock2420_data.c
View File

@ -1898,18 +1898,6 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
CLK("omap_timer.1", "fck", &gpt1_fck, CK_242X),
CLK("omap_timer.2", "fck", &gpt2_fck, CK_242X),
CLK("omap_timer.3", "fck", &gpt3_fck, CK_242X),
CLK("omap_timer.4", "fck", &gpt4_fck, CK_242X),
CLK("omap_timer.5", "fck", &gpt5_fck, CK_242X),
CLK("omap_timer.6", "fck", &gpt6_fck, CK_242X),
CLK("omap_timer.7", "fck", &gpt7_fck, CK_242X),
CLK("omap_timer.8", "fck", &gpt8_fck, CK_242X),
CLK("omap_timer.9", "fck", &gpt9_fck, CK_242X),
CLK("omap_timer.10", "fck", &gpt10_fck, CK_242X),
CLK("omap_timer.11", "fck", &gpt11_fck, CK_242X),
CLK("omap_timer.12", "fck", &gpt12_fck, CK_242X),
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),

12
arch/arm/mach-omap2/clock2430_data.c
View File

@ -1998,18 +1998,6 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
CLK("omap_timer.1", "fck", &gpt1_fck, CK_243X),
CLK("omap_timer.2", "fck", &gpt2_fck, CK_243X),
CLK("omap_timer.3", "fck", &gpt3_fck, CK_243X),
CLK("omap_timer.4", "fck", &gpt4_fck, CK_243X),
CLK("omap_timer.5", "fck", &gpt5_fck, CK_243X),
CLK("omap_timer.6", "fck", &gpt6_fck, CK_243X),
CLK("omap_timer.7", "fck", &gpt7_fck, CK_243X),
CLK("omap_timer.8", "fck", &gpt8_fck, CK_243X),
CLK("omap_timer.9", "fck", &gpt9_fck, CK_243X),
CLK("omap_timer.10", "fck", &gpt10_fck, CK_243X),
CLK("omap_timer.11", "fck", &gpt11_fck, CK_243X),
CLK("omap_timer.12", "fck", &gpt12_fck, CK_243X),
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),

12
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3464,18 +3464,6 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
CLK("omap_timer.1", "fck", &gpt1_fck, CK_3XXX),
CLK("omap_timer.2", "fck", &gpt2_fck, CK_3XXX),
CLK("omap_timer.3", "fck", &gpt3_fck, CK_3XXX),
CLK("omap_timer.4", "fck", &gpt4_fck, CK_3XXX),
CLK("omap_timer.5", "fck", &gpt5_fck, CK_3XXX),
CLK("omap_timer.6", "fck", &gpt6_fck, CK_3XXX),
CLK("omap_timer.7", "fck", &gpt7_fck, CK_3XXX),
CLK("omap_timer.8", "fck", &gpt8_fck, CK_3XXX),
CLK("omap_timer.9", "fck", &gpt9_fck, CK_3XXX),
CLK("omap_timer.10", "fck", &gpt10_fck, CK_3XXX),
CLK("omap_timer.11", "fck", &gpt11_fck, CK_3XXX),
CLK("omap_timer.12", "fck", &gpt12_fck, CK_3XXX),
CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),

7
arch/arm/mach-omap2/clock44xx.h
View File

@ -8,6 +8,13 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
/*
* OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is
* set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM
* vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters")
*/
#define OMAP4430_REGM4XEN_MULT 4
int omap4xxx_clk_init(void);
#endif

43
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -270,8 +270,8 @@ static struct clk dpll_abe_ck = {
.dpll_data = &dpll_abe_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap4_dpll_regm4xen_recalc,
.round_rate = &omap4_dpll_regm4xen_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
};
@ -1195,11 +1195,25 @@ static struct clk l4_wkup_clk_mux_ck = {
.recalc = &omap2_clksel_recalc,
};
static const struct clksel_rate div2_2to1_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
{ .div = 0 },
};
static const struct clksel ocp_abe_iclk_div[] = {
{ .parent = &aess_fclk, .rates = div2_2to1_rates },
{ .parent = NULL },
};
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
.clksel = ocp_abe_iclk_div,
.clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
.ops = &clkops_null,
.recalc = &followparent_recalc,
.recalc = &omap2_clksel_recalc,
};
static struct clk per_abe_24m_fclk = {
@ -1398,9 +1412,9 @@ static struct clk dss_dss_clk = {
};
static const struct clksel_rate div3_8to32_rates[] = {
{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
{ .div = 8, .val = 0, .flags = RATE_IN_4460 },
{ .div = 16, .val = 1, .flags = RATE_IN_4460 },
{ .div = 32, .val = 2, .flags = RATE_IN_4460 },
{ .div = 0 },
};
@ -3363,17 +3377,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK("omap_timer.1", "fck", &timer1_fck, CK_443X),
CLK("omap_timer.2", "fck", &timer2_fck, CK_443X),
CLK("omap_timer.3", "fck", &timer3_fck, CK_443X),
CLK("omap_timer.4", "fck", &timer4_fck, CK_443X),
CLK("omap_timer.5", "fck", &timer5_fck, CK_443X),
CLK("omap_timer.6", "fck", &timer6_fck, CK_443X),
CLK("omap_timer.7", "fck", &timer7_fck, CK_443X),
CLK("omap_timer.8", "fck", &timer8_fck, CK_443X),
CLK("omap_timer.9", "fck", &timer9_fck, CK_443X),
CLK("omap_timer.10", "fck", &timer10_fck, CK_443X),
CLK("omap_timer.11", "fck", &timer11_fck, CK_443X),
CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
@ -3403,12 +3406,12 @@ int __init omap4xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg;
if (cpu_is_omap44xx()) {
if (cpu_is_omap443x()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
} else if (cpu_is_omap446x()) {
cpu_mask = RATE_IN_4460;
cpu_clkflg = CK_446X;
cpu_mask = RATE_IN_4460 | RATE_IN_4430;
cpu_clkflg = CK_446X | CK_443X;
} else {
return 0;
}

17
arch/arm/mach-omap2/devices.c
View File

@ -318,18 +318,10 @@ static inline void omap_init_audio(void) {}
#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
static struct omap_device_pm_latency omap_mcpdm_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
static void omap_init_mcpdm(void)
{
struct omap_hwmod *oh;
struct omap_device *od;
struct platform_device *pdev;
oh = omap_hwmod_lookup("mcpdm");
if (!oh) {
@ -337,11 +329,8 @@ static void omap_init_mcpdm(void)
return;
}
od = omap_device_build("omap-mcpdm", -1, oh, NULL, 0,
omap_mcpdm_latency,
ARRAY_SIZE(omap_mcpdm_latency), 0);
if (IS_ERR(od))
printk(KERN_ERR "Could not build omap_device for omap-mcpdm-dai\n");
pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
}
#else
static inline void omap_init_mcpdm(void) {}

9
arch/arm/mach-omap2/dpll3xxx.c
View File

@ -390,7 +390,8 @@ int omap3_noncore_dpll_enable(struct clk *clk)
* propagating?
*/
if (!r)
clk->rate = omap2_get_dpll_rate(clk);
clk->rate = (clk->recalc) ? clk->recalc(clk) :
omap2_get_dpll_rate(clk);
return r;
}
@ -424,6 +425,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *new_parent = NULL;
unsigned long hw_rate;
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
@ -435,7 +437,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
if (!dd)
return -EINVAL;
if (rate == omap2_get_dpll_rate(clk))
hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
if (rate == hw_rate)
return 0;
/*
@ -455,7 +458,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
new_parent = dd->clk_bypass;
} else {
if (dd->last_rounded_rate != rate)
omap2_dpll_round_rate(clk, rate);
rate = clk->round_rate(clk, rate);
if (dd->last_rounded_rate == 0)
return -EINVAL;

69
arch/arm/mach-omap2/dpll44xx.c
View File

@ -19,6 +19,7 @@
#include <plat/clock.h>
#include "clock.h"
#include "clock44xx.h"
#include "cm-regbits-44xx.h"
/* Supported only on OMAP4 */
@ -82,3 +83,71 @@ const struct clkops clkops_omap4_dpllmx_ops = {
.deny_idle = omap4_dpllmx_deny_gatectrl,
};
/**
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
* @clk: struct clk * of the DPLL to compute the rate for
*
* Compute the output rate for the OMAP4 DPLL represented by @clk.
* Takes the REGM4XEN bit into consideration, which is needed for the
* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
* upon success, or 0 upon error.
*/
unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
{
u32 v;
unsigned long rate;
struct dpll_data *dd;
if (!clk || !clk->dpll_data)
return 0;
dd = clk->dpll_data;
rate = omap2_get_dpll_rate(clk);
/* regm4xen adds a multiplier of 4 to DPLL calculations */
v = __raw_readl(dd->control_reg);
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
rate *= OMAP4430_REGM4XEN_MULT;
return rate;
}
/**
* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
* @clk: struct clk * of the DPLL to round a rate for
* @target_rate: the desired rate of the DPLL
*
* Compute the rate that would be programmed into the DPLL hardware
* for @clk if set_rate() were to be provided with the rate
* @target_rate. Takes the REGM4XEN bit into consideration, which is
* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
* ~0 if an error occurred in omap2_dpll_round_rate().
*/
long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
{
u32 v;
struct dpll_data *dd;
long r;
if (!clk || !clk->dpll_data)
return -EINVAL;
dd = clk->dpll_data;
/* regm4xen adds a multiplier of 4 to DPLL calculations */
v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
if (v)
target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
r = omap2_dpll_round_rate(clk, target_rate);
if (r == ~0)
return r;
if (v)
clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
return clk->dpll_data->last_rounded_rate;
}

1
arch/arm/mach-omap2/dsp.c
View File

@ -18,6 +18,7 @@
* of the OMAP PM core code.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"

16
arch/arm/mach-omap2/hsmmc.c
View File

@ -129,15 +129,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
* card with Vcc regulator (from twl4030 or whatever). OMAP has both
* 1.8V and 3.0V modes, controlled by the PBIAS register.
*
* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
* is most naturally TWL VSIM; those pins also use PBIAS.
*
* FIXME handle VMMC1A as needed ...
*/
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK);
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
@ -172,12 +168,6 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
} else {
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
}
@ -489,7 +479,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);

5
arch/arm/mach-omap2/id.c
View File

@ -187,8 +187,11 @@ static void __init omap3_check_features(void)
OMAP3_CHECK_FEATURE(status, ISP);
if (cpu_is_omap3630())
omap_features |= OMAP3_HAS_192MHZ_CLK;
if (!cpu_is_omap3505() && !cpu_is_omap3517())
if (cpu_is_omap3430() || cpu_is_omap3630())
omap_features |= OMAP3_HAS_IO_WAKEUP;
if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
omap_rev() == OMAP3430_REV_ES3_1_2)
omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
omap_features |= OMAP3_HAS_SDRC;

8
arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
View File

@ -941,10 +941,10 @@
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_DSI1_PIPD_SHIFT 19
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI2_PIPD_SHIFT 14
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
#define OMAP4_DSI2_PIPD_SHIFT 19
#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI1_PIPD_SHIFT 14
#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
/* CONTROL_MCBSPLP */
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31

6
arch/arm/mach-omap2/io.c
View File

@ -359,6 +359,7 @@ static void __init omap_hwmod_init_postsetup(void)
omap_pm_if_early_init();
}
#ifdef CONFIG_ARCH_OMAP2
void __init omap2420_init_early(void)
{
omap2_set_globals_242x();
@ -382,11 +383,13 @@ void __init omap2430_init_early(void)
omap_hwmod_init_postsetup();
omap2430_clk_init();
}
#endif
/*
* Currently only board-omap3beagle.c should call this because of the
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
{
omap2_set_globals_3xxx();
@ -430,7 +433,9 @@ void __init ti816x_init_early(void)
omap_hwmod_init_postsetup();
omap3xxx_clk_init();
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
omap2_set_globals_443x();
@ -442,6 +447,7 @@ void __init omap4430_init_early(void)
omap_hwmod_init_postsetup();
omap4xxx_clk_init();
}
#endif
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)

1
arch/arm/mach-omap2/mailbox.c
View File

@ -10,6 +10,7 @@
* for more details.
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>

1
arch/arm/mach-omap2/omap-iommu.c
View File

@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <plat/iommu.h>

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2625,7 +2625,7 @@ ohsps_unlock:
* Returns the context loss count of the powerdomain assocated with @oh
* upon success, or zero if no powerdomain exists for @oh.
*/
u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
{
struct powerdomain *pwrdm;
int ret = 0;

17
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -3159,7 +3159,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_mmc2_hwmod,
&omap3xxx_mmc3_hwmod,
&omap3xxx_mpu_hwmod,
&omap3xxx_iva_hwmod,
&omap3xxx_timer1_hwmod,
&omap3xxx_timer2_hwmod,
@ -3188,8 +3187,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_i2c1_hwmod,
&omap3xxx_i2c2_hwmod,
&omap3xxx_i2c3_hwmod,
&omap34xx_sr1_hwmod,
&omap34xx_sr2_hwmod,
/* gpio class */
&omap3xxx_gpio1_hwmod,
@ -3211,8 +3208,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_mcbsp2_sidetone_hwmod,
&omap3xxx_mcbsp3_sidetone_hwmod,
/* mailbox class */
&omap3xxx_mailbox_hwmod,
/* mcspi class */
&omap34xx_mcspi1,
@ -3225,31 +3220,39 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
/* 3430ES1-only hwmods */
static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
&omap3xxx_iva_hwmod,
&omap3430es1_dss_core_hwmod,
&omap3xxx_mailbox_hwmod,
NULL
};
/* 3430ES2+-only hwmods */
static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
&omap3xxx_iva_hwmod,
&omap3xxx_dss_core_hwmod,
&omap3xxx_usbhsotg_hwmod,
&omap3xxx_mailbox_hwmod,
NULL
};
/* 34xx-only hwmods (all ES revisions) */
static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
&omap3xxx_iva_hwmod,
&omap34xx_sr1_hwmod,
&omap34xx_sr2_hwmod,
&omap3xxx_mailbox_hwmod,
NULL
};
/* 36xx-only hwmods (all ES revisions) */
static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
&omap3xxx_iva_hwmod,
&omap3xxx_uart4_hwmod,
&omap3xxx_dss_core_hwmod,
&omap36xx_sr1_hwmod,
&omap36xx_sr2_hwmod,
&omap3xxx_usbhsotg_hwmod,
&omap3xxx_mailbox_hwmod,
NULL
};
@ -3267,7 +3270,7 @@ int __init omap3xxx_hwmod_init(void)
/* Register hwmods common to all OMAP3 */
r = omap_hwmod_register(omap3xxx_hwmods);
if (!r)
if (r < 0)
return r;
rev = omap_rev();
@ -3292,7 +3295,7 @@ int __init omap3xxx_hwmod_init(void)
};
r = omap_hwmod_register(h);
if (!r)
if (r < 0)
return r;
/*

1
arch/arm/mach-omap2/omap_l3_noc.c
View File

@ -20,6 +20,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>

68
arch/arm/mach-omap2/pm34xx.c
View File

@ -99,31 +99,27 @@ static void omap3_enable_io_chain(void)
{
int timeout = 0;
if (omap_rev() >= OMAP3430_REV_ES3_1) {
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
/* Do a readback to assure write has been done */
omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
/* Do a readback to assure write has been done */
omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
OMAP3430_ST_IO_CHAIN_MASK)) {
timeout++;
if (timeout > 1000) {
printk(KERN_ERR "Wake up daisy chain "
"activation failed.\n");
return;
}
omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
WKUP_MOD, PM_WKEN);
while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
OMAP3430_ST_IO_CHAIN_MASK)) {
timeout++;
if (timeout > 1000) {
pr_err("Wake up daisy chain activation failed.\n");
return;
}
omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
WKUP_MOD, PM_WKEN);
}
}
static void omap3_disable_io_chain(void)
{
if (omap_rev() >= OMAP3430_REV_ES3_1)
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
}
static void omap3_core_save_context(void)
@ -363,7 +359,6 @@ void omap_sram_idle(void)
printk(KERN_ERR "Invalid mpu state in sram_idle\n");
return;
}
pwrdm_pre_transition();
/* NEON control */
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
@ -376,7 +371,8 @@ void omap_sram_idle(void)
(per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)) {
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
omap3_enable_io_chain();
if (omap3_has_io_chain_ctrl())
omap3_enable_io_chain();
}
/* Block console output in case it is on one of the OMAP UARTs */
@ -386,6 +382,8 @@ void omap_sram_idle(void)
if (!console_trylock())
goto console_still_active;
pwrdm_pre_transition();
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
@ -409,13 +407,14 @@ void omap_sram_idle(void)
omap3_intc_prepare_idle();
/*
* On EMU/HS devices ROM code restores a SRDC value
* from scratchpad which has automatic self refresh on timeout
* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
* Hence store/restore the SDRC_POWER register here.
*/
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
omap_type() != OMAP2_DEVICE_TYPE_GP &&
* On EMU/HS devices ROM code restores a SRDC value
* from scratchpad which has automatic self refresh on timeout
* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
* Hence store/restore the SDRC_POWER register here.
*/
if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
core_next_state == PWRDM_POWER_OFF)
sdrc_pwr = sdrc_read_reg(SDRC_POWER);
@ -432,8 +431,9 @@ void omap_sram_idle(void)
omap34xx_do_sram_idle(save_state);
/* Restore normal SDRC POWER settings */
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
omap_type() != OMAP2_DEVICE_TYPE_GP &&
if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
core_next_state == PWRDM_POWER_OFF)
sdrc_write_reg(sdrc_pwr, SDRC_POWER);
@ -455,6 +455,8 @@ void omap_sram_idle(void)
}
omap3_intc_resume_idle();
pwrdm_post_transition();
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
@ -475,11 +477,10 @@ console_still_active:
core_next_state < PWRDM_POWER_ON)) {
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
PM_WKEN);
omap3_disable_io_chain();
if (omap3_has_io_chain_ctrl())
omap3_disable_io_chain();
}
pwrdm_post_transition();
clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
}
@ -870,6 +871,9 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
if (!omap3_has_io_chain_ctrl())
pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
pm_errata_configure();
/* XXX prcm_setup_regs needs to be before enabling hw

14
arch/arm/mach-omap2/powerdomain.c
View File

@ -1002,16 +1002,16 @@ int pwrdm_post_transition(void)
* @pwrdm: struct powerdomain * to wait for
*
* Context loss count is the sum of powerdomain off-mode counter, the
* logic off counter and the per-bank memory off counter. Returns 0
* logic off counter and the per-bank memory off counter. Returns negative
* (and WARNs) upon error, otherwise, returns the context loss count.
*/
u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
{
int i, count;
if (!pwrdm) {
WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
return 0;
return -ENODEV;
}
count = pwrdm->state_counter[PWRDM_POWER_OFF];
@ -1020,7 +1020,13 @@ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
for (i = 0; i < pwrdm->banks; i++)
count += pwrdm->ret_mem_off_counter[i];
pr_debug("powerdomain: %s: context loss count = %u\n",
/*
* Context loss count has to be a non-negative value. Clear the sign
* bit to get a value range from 0 to INT_MAX.
*/
count &= INT_MAX;
pr_debug("powerdomain: %s: context loss count = %d\n",
pwrdm->name, count);
return count;

2
arch/arm/mach-omap2/powerdomain.h
View File

@ -217,7 +217,7 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
int pwrdm_pre_transition(void);
int pwrdm_post_transition(void);
int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
extern void omap242x_powerdomains_init(void);

1
arch/arm/mach-omap2/smartreflex.c
View File

@ -17,6 +17,7 @@
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/io.h>

12
arch/arm/mach-omap2/timer.c
View File

@ -408,14 +408,6 @@ static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
return ret;
}
struct omap_device_pm_latency omap2_dmtimer_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
/**
* omap_timer_init - build and register timer device with an
* associated timer hwmod
@ -477,9 +469,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
#endif
pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
omap2_dmtimer_latency,
ARRAY_SIZE(omap2_dmtimer_latency),
0);
NULL, 0, 0);
if (IS_ERR(pdev)) {
pr_err("%s: Can't build omap_device for %s: %s.\n",

38
arch/arm/mach-omap2/usb-musb.c
View File

@ -60,44 +60,6 @@ static struct musb_hdrc_platform_data musb_plat = {
static u64 musb_dmamask = DMA_BIT_MASK(32);
static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
{
switch (board_data->interface_type) {
case MUSB_INTERFACE_UTMI:
omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT);
omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT);
break;
case MUSB_INTERFACE_ULPI:
omap_mux_init_signal("usba0_ulpiphy_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_stp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usba0_ulpiphy_dat7",
OMAP_PIN_INPUT_PULLDOWN);
break;
default:
break;
}
}
static struct omap_musb_board_data musb_default_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
.mode = MUSB_OTG,

1
arch/arm/plat-omap/dmtimer.c
View File

@ -35,6 +35,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>

2
arch/arm/plat-omap/i2c.c
View File

@ -184,7 +184,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
NULL, 0, 0);
WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
return PTR_ERR(pdev);
return PTR_RET(pdev);
}
#else
static inline int omap2_i2c_add_bus(int bus_id)

17
arch/arm/plat-omap/include/plat/cpu.h
View File

@ -399,6 +399,13 @@ void omap2_check_revision(void);
/*
* Runtime detection of OMAP3 features
*
* OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
* family have OS-level control over the I/O chain clock. This is
* to avoid a window during which wakeups could potentially be lost
* during powerdomain transitions. If this bit is set, it
* indicates that the chip does support OS-level control of this
* feature.
*/
extern u32 omap_features;
@ -410,9 +417,10 @@ extern u32 omap_features;
#define OMAP3_HAS_192MHZ_CLK BIT(5)
#define OMAP3_HAS_IO_WAKEUP BIT(6)
#define OMAP3_HAS_SDRC BIT(7)
#define OMAP4_HAS_MPU_1GHZ BIT(8)
#define OMAP4_HAS_MPU_1_2GHZ BIT(9)
#define OMAP4_HAS_MPU_1_5GHZ BIT(10)
#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8)
#define OMAP4_HAS_MPU_1GHZ BIT(9)
#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
#define OMAP4_HAS_MPU_1_5GHZ BIT(11)
#define OMAP3_HAS_FEATURE(feat,flag) \
@ -429,12 +437,11 @@ OMAP3_HAS_FEATURE(isp, ISP)
OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
OMAP3_HAS_FEATURE(sdrc, SDRC)
OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
/*
* Runtime detection of OMAP4 features
*/
extern u32 omap_features;
#define OMAP4_HAS_FEATURE(feat, flag) \
static inline unsigned int omap4_has_ ##feat(void) \
{ \

4
arch/arm/plat-omap/include/plat/dmtimer.h
View File

@ -104,7 +104,7 @@ struct dmtimer_platform_data {
bool loses_context;
u32 (*get_context_loss_count)(struct device *dev);
int (*get_context_loss_count)(struct device *dev);
};
struct omap_dm_timer *omap_dm_timer_request(void);
@ -279,7 +279,7 @@ struct omap_dm_timer {
struct platform_device *pdev;
struct list_head node;
u32 (*get_context_loss_count)(struct device *dev);
int (*get_context_loss_count)(struct device *dev);
};
int omap_dm_timer_prepare(struct omap_dm_timer *timer);

123
arch/arm/plat-omap/include/plat/omap-alsa.h
View File

@ -1,123 +0,0 @@
/*
* arch/arm/plat-omap/include/mach/omap-alsa.h
*
* Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
*
* Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
*
* Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
* Written by Daniel Petrini, David Cohen, Anderson Briglia
* {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* History
* -------
*
* 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
* original version based in sa1100 driver
* and omap oss driver.
*/
#ifndef __OMAP_ALSA_H
#define __OMAP_ALSA_H
#include <plat/dma.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <plat/mcbsp.h>
#include <linux/platform_device.h>
#define DMA_BUF_SIZE (1024 * 8)
/*
* Buffer management for alsa and dma
*/
struct audio_stream {
char *id; /* identification string */
int stream_id; /* numeric identification */
int dma_dev; /* dma number of that device */
int *lch; /* Chain of channels this stream is linked to */
char started; /* to store if the chain was started or not */
int dma_q_head; /* DMA Channel Q Head */
int dma_q_tail; /* DMA Channel Q Tail */
char dma_q_count; /* DMA Channel Q Count */
int active:1; /* we are using this stream for transfer now */
int period; /* current transfer period */
int periods; /* current count of periods registerd in the DMA engine */
spinlock_t dma_lock; /* for locking in DMA operations */
struct snd_pcm_substream *stream; /* the pcm stream */
unsigned linked:1; /* dma channels linked */
int offset; /* store start position of the last period in the alsa buffer */
int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
};
/*
* Alsa card structure for aic23
*/
struct snd_card_omap_codec {
struct snd_card *card;
struct snd_pcm *pcm;
long samplerate;
struct audio_stream s[2]; /* playback & capture */
};
/* Codec specific information and function pointers.
* Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
* are responsible for defining the function pointers.
*/
struct omap_alsa_codec_config {
char *name;
struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
struct snd_pcm_hw_constraint_list *hw_constraints_rates;
struct snd_pcm_hardware *snd_omap_alsa_playback;
struct snd_pcm_hardware *snd_omap_alsa_capture;
void (*codec_configure_dev)(void);
void (*codec_set_samplerate)(long);
void (*codec_clock_setup)(void);
int (*codec_clock_on)(void);
int (*codec_clock_off)(void);
int (*get_default_samplerate)(void);
};
/*********** Mixer function prototypes *************************/
int snd_omap_mixer(struct snd_card_omap_codec *);
void snd_omap_init_mixer(void);
#ifdef CONFIG_PM
void snd_omap_suspend_mixer(void);
void snd_omap_resume_mixer(void);
#endif
int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
int snd_omap_alsa_remove(struct platform_device *pdev);
#ifdef CONFIG_PM
int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
int snd_omap_alsa_resume(struct platform_device *pdev);
#else
#define snd_omap_alsa_suspend NULL
#define snd_omap_alsa_resume NULL
#endif
void callback_omap_alsa_sound_dma(void *);
#endif

4
arch/arm/plat-omap/include/plat/omap-pm.h
View File

@ -342,9 +342,9 @@ unsigned long omap_pm_cpu_get_freq(void);
* driver must restore device context. If the number of context losses
* exceeds the maximum positive integer, the function will wrap to 0 and
* continue counting. Returns the number of context losses for this device,
* or zero upon error.
* or negative value upon error.
*/
u32 omap_pm_get_dev_context_loss_count(struct device *dev);
int omap_pm_get_dev_context_loss_count(struct device *dev);
void omap_pm_enable_off_mode(void);
void omap_pm_disable_off_mode(void);

2
arch/arm/plat-omap/include/plat/omap_device.h
View File

@ -107,7 +107,7 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name);
int omap_device_align_pm_lat(struct platform_device *pdev,
u32 new_wakeup_lat_limit);
struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
u32 omap_device_get_context_loss_count(struct platform_device *pdev);
int omap_device_get_context_loss_count(struct platform_device *pdev);
/* Other */

2
arch/arm/plat-omap/include/plat/omap_hwmod.h
View File

@ -600,7 +600,7 @@ int omap_hwmod_for_each_by_class(const char *classname,
void *user);
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);

24
arch/arm/plat-omap/omap-pm-noop.c
View File

@ -27,7 +27,7 @@
#include <plat/omap_device.h>
static bool off_mode_enabled;
static u32 dummy_context_loss_counter;
static int dummy_context_loss_counter;
/*
* Device-driver-originated constraints (via board-*.c files)
@ -311,22 +311,32 @@ void omap_pm_disable_off_mode(void)
#ifdef CONFIG_ARCH_OMAP2PLUS
u32 omap_pm_get_dev_context_loss_count(struct device *dev)
int omap_pm_get_dev_context_loss_count(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
u32 count;
int count;
if (WARN_ON(!dev))
return 0;
return -ENODEV;
if (dev->parent == &omap_device_parent) {
count = omap_device_get_context_loss_count(pdev);
} else {
WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
dev_name(dev));
if (off_mode_enabled)
dummy_context_loss_counter++;
count = dummy_context_loss_counter;
if (off_mode_enabled) {
count++;
/*
* Context loss count has to be a non-negative value.
* Clear the sign bit to get a value range from 0 to
* INT_MAX.
*/
count &= INT_MAX;
dummy_context_loss_counter = count;
}
}
pr_debug("OMAP PM: context loss count for dev %s = %d\n",
@ -337,7 +347,7 @@ u32 omap_pm_get_dev_context_loss_count(struct device *dev)
#else
u32 omap_pm_get_dev_context_loss_count(struct device *dev)
int omap_pm_get_dev_context_loss_count(struct device *dev)
{
return dummy_context_loss_counter;
}

3
arch/arm/plat-omap/omap_device.c
View File

@ -78,6 +78,7 @@
#undef DEBUG
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
@ -426,7 +427,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
* return the context loss counter for that hwmod, otherwise return
* zero.
*/
u32 omap_device_get_context_loss_count(struct platform_device *pdev)
int omap_device_get_context_loss_count(struct platform_device *pdev)
{
struct omap_device *od;
u32 ret = 0;