x86: Coding style fixes to arch/x86/oprofile/op_model_p4.c
A coding style patch to arch/x86/oprofile/op_model_p4.c that removes 87 errors and 4 warnings. Before: total: 89 errors, 13 warnings, 722 lines checked After: total: 2 errors, 9 warnings, 721 lines checked Compile tested, binary verified as follow: paolo@paolo-desktop:~/linux.trees.git$ size /tmp/op_model_p4.o.* text data bss dec hex filename 2691 968 32 3691 e6b /tmp/op_model_p4.o.after 2691 968 32 3691 e6b /tmp/op_model_p4.o.before paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/op_model_p4.o.* 8c1c9823bab33333e1f7f76574e62561 /tmp/op_model_p4.o.after 8c1c9823bab33333e1f7f76574e62561 /tmp/op_model_p4.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Cc: robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
Ingo Molnar
parent
a7f5aaf36d
commit
20211e4d34
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@ -10,11 +10,12 @@
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#include <linux/oprofile.h>
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#include <linux/smp.h>
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#include <linux/ptrace.h>
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#include <linux/nmi.h>
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#include <asm/msr.h>
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#include <asm/ptrace.h>
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#include <asm/fixmap.h>
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#include <asm/apic.h>
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#include <asm/nmi.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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@ -40,7 +41,7 @@ static unsigned int num_controls = NUM_CONTROLS_NON_HT;
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static inline void setup_num_counters(void)
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{
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#ifdef CONFIG_SMP
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if (smp_num_siblings == 2){
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if (smp_num_siblings == 2) {
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num_counters = NUM_COUNTERS_HT2;
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num_controls = NUM_CONTROLS_HT2;
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}
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@ -86,7 +87,7 @@ struct p4_event_binding {
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#define CTR_FLAME_2 (1 << 6)
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#define CTR_IQ_5 (1 << 7)
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static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
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static struct p4_counter_binding p4_counters[NUM_COUNTERS_NON_HT] = {
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{ CTR_BPU_0, MSR_P4_BPU_PERFCTR0, MSR_P4_BPU_CCCR0 },
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{ CTR_MS_0, MSR_P4_MS_PERFCTR0, MSR_P4_MS_CCCR0 },
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{ CTR_FLAME_0, MSR_P4_FLAME_PERFCTR0, MSR_P4_FLAME_CCCR0 },
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@ -97,32 +98,32 @@ static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
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{ CTR_IQ_5, MSR_P4_IQ_PERFCTR5, MSR_P4_IQ_CCCR5 }
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};
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#define NUM_UNUSED_CCCRS NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT
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#define NUM_UNUSED_CCCRS (NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT)
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/* p4 event codes in libop/op_event.h are indices into this table. */
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static struct p4_event_binding p4_events[NUM_EVENTS] = {
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{ /* BRANCH_RETIRED */
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0x05, 0x06,
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0x05, 0x06,
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{ {CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* MISPRED_BRANCH_RETIRED */
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0x04, 0x03,
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0x04, 0x03,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR0},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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{ /* TC_DELIVER_MODE */
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0x01, 0x01,
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{ { CTR_MS_0, MSR_P4_TC_ESCR0},
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{ { CTR_MS_0, MSR_P4_TC_ESCR0},
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{ CTR_MS_2, MSR_P4_TC_ESCR1} }
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},
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{ /* BPU_FETCH_REQUEST */
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0x00, 0x03,
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0x00, 0x03,
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{ { CTR_BPU_0, MSR_P4_BPU_ESCR0},
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{ CTR_BPU_2, MSR_P4_BPU_ESCR1} }
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},
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@ -146,7 +147,7 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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},
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{ /* LOAD_PORT_REPLAY */
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0x02, 0x04,
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0x02, 0x04,
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{ { CTR_FLAME_0, MSR_P4_SAAT_ESCR0},
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{ CTR_FLAME_2, MSR_P4_SAAT_ESCR1} }
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},
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@ -170,43 +171,43 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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},
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{ /* BSQ_CACHE_REFERENCE */
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0x07, 0x0c,
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0x07, 0x0c,
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{ { CTR_BPU_0, MSR_P4_BSU_ESCR0},
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{ CTR_BPU_2, MSR_P4_BSU_ESCR1} }
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},
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{ /* IOQ_ALLOCATION */
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0x06, 0x03,
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0x06, 0x03,
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ 0, 0 } }
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},
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{ /* IOQ_ACTIVE_ENTRIES */
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0x06, 0x1a,
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0x06, 0x1a,
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{ { CTR_BPU_2, MSR_P4_FSB_ESCR1},
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{ 0, 0 } }
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},
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{ /* FSB_DATA_ACTIVITY */
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0x06, 0x17,
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0x06, 0x17,
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ CTR_BPU_2, MSR_P4_FSB_ESCR1} }
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},
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{ /* BSQ_ALLOCATION */
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0x07, 0x05,
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0x07, 0x05,
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{ { CTR_BPU_0, MSR_P4_BSU_ESCR0},
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{ 0, 0 } }
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},
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{ /* BSQ_ACTIVE_ENTRIES */
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0x07, 0x06,
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{ { CTR_BPU_2, MSR_P4_BSU_ESCR1 /* guess */},
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{ { CTR_BPU_2, MSR_P4_BSU_ESCR1 /* guess */},
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{ 0, 0 } }
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},
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{ /* X87_ASSIST */
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0x05, 0x03,
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0x05, 0x03,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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@ -216,21 +217,21 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* PACKED_SP_UOP */
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0x01, 0x08,
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0x01, 0x08,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* PACKED_DP_UOP */
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0x01, 0x0c,
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0x01, 0x0c,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* SCALAR_SP_UOP */
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0x01, 0x0a,
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0x01, 0x0a,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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@ -242,31 +243,31 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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},
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{ /* 64BIT_MMX_UOP */
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0x01, 0x02,
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0x01, 0x02,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* 128BIT_MMX_UOP */
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0x01, 0x1a,
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0x01, 0x1a,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* X87_FP_UOP */
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0x01, 0x04,
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0x01, 0x04,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* X87_SIMD_MOVES_UOP */
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0x01, 0x2e,
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0x01, 0x2e,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* MACHINE_CLEAR */
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0x05, 0x02,
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0x05, 0x02,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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@ -276,9 +277,9 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ CTR_BPU_2, MSR_P4_FSB_ESCR1} }
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},
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{ /* TC_MS_XFER */
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0x00, 0x05,
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0x00, 0x05,
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{ { CTR_MS_0, MSR_P4_MS_ESCR0},
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{ CTR_MS_2, MSR_P4_MS_ESCR1} }
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},
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@ -308,7 +309,7 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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},
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{ /* INSTR_RETIRED */
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0x04, 0x02,
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0x04, 0x02,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR0},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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@ -319,14 +320,14 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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{ /* UOP_TYPE */
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0x02, 0x02,
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{ /* UOP_TYPE */
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0x02, 0x02,
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{ { CTR_IQ_4, MSR_P4_RAT_ESCR0},
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{ CTR_IQ_5, MSR_P4_RAT_ESCR1} }
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},
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{ /* RETIRED_MISPRED_BRANCH_TYPE */
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0x02, 0x05,
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0x02, 0x05,
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{ { CTR_MS_0, MSR_P4_TBPU_ESCR0},
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{ CTR_MS_2, MSR_P4_TBPU_ESCR1} }
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},
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@ -349,8 +350,8 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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#define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1))
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#define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25))
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#define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9))
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#define ESCR_READ(escr,high,ev,i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
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#define ESCR_WRITE(escr,high,ev,i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
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#define ESCR_READ(escr, high, ev, i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
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#define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
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#define CCCR_RESERVED_BITS 0x38030FFF
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#define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS)
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@ -360,15 +361,15 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
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#define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27))
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#define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12))
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#define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12))
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#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
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#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
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#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
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#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
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#define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))
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#define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))
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#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
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#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l,h,i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h));} while (0)
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#define CTR_WRITE(l,i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
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#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
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#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)
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#define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)
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#define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))
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@ -380,7 +381,7 @@ static unsigned int get_stagger(void)
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#ifdef CONFIG_SMP
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int cpu = smp_processor_id();
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return (cpu != first_cpu(per_cpu(cpu_sibling_map, cpu)));
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#endif
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#endif
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return 0;
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}
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@ -395,25 +396,23 @@ static unsigned long reset_value[NUM_COUNTERS_NON_HT];
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static void p4_fill_in_addresses(struct op_msrs * const msrs)
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{
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unsigned int i;
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unsigned int i;
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unsigned int addr, cccraddr, stag;
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setup_num_counters();
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stag = get_stagger();
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/* initialize some registers */
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for (i = 0; i < num_counters; ++i) {
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for (i = 0; i < num_counters; ++i)
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < num_controls; ++i) {
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for (i = 0; i < num_controls; ++i)
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msrs->controls[i].addr = 0;
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}
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/* the counter & cccr registers we pay attention to */
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for (i = 0; i < num_counters; ++i) {
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addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
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cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address;
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if (reserve_perfctr_nmi(addr)){
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if (reserve_perfctr_nmi(addr)) {
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msrs->counters[i].addr = addr;
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msrs->controls[i].addr = cccraddr;
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}
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@ -447,22 +446,22 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
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if (reserve_evntsel_nmi(addr))
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msrs->controls[i].addr = addr;
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}
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for (addr = MSR_P4_MS_ESCR0 + stag;
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addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) {
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addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) {
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if (reserve_evntsel_nmi(addr))
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msrs->controls[i].addr = addr;
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}
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for (addr = MSR_P4_IX_ESCR0 + stag;
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addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) {
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addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) {
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if (reserve_evntsel_nmi(addr))
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msrs->controls[i].addr = addr;
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}
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/* there are 2 remaining non-contiguously located ESCRs */
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if (num_counters == NUM_COUNTERS_NON_HT) {
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if (num_counters == NUM_COUNTERS_NON_HT) {
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/* standard non-HT CPUs handle both remaining ESCRs*/
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if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5))
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msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
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@ -498,20 +497,20 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
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unsigned int stag;
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stag = get_stagger();
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/* convert from counter *number* to counter *bit* */
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counter_bit = 1 << VIRT_CTR(stag, ctr);
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/* find our event binding structure. */
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if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) {
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printk(KERN_ERR
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"oprofile: P4 event code 0x%lx out of range\n",
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printk(KERN_ERR
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"oprofile: P4 event code 0x%lx out of range\n",
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counter_config[ctr].event);
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return;
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}
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ev = &(p4_events[counter_config[ctr].event - 1]);
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for (i = 0; i < maxbind; i++) {
|
||||
if (ev->bindings[i].virt_counter & counter_bit) {
|
||||
|
||||
|
|
@ -526,25 +525,24 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
|
|||
ESCR_SET_OS_1(escr, counter_config[ctr].kernel);
|
||||
}
|
||||
ESCR_SET_EVENT_SELECT(escr, ev->event_select);
|
||||
ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);
|
||||
ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);
|
||||
ESCR_WRITE(escr, high, ev, i);
|
||||
|
||||
|
||||
/* modify CCCR */
|
||||
CCCR_READ(cccr, high, VIRT_CTR(stag, ctr));
|
||||
CCCR_CLEAR(cccr);
|
||||
CCCR_SET_REQUIRED_BITS(cccr);
|
||||
CCCR_SET_ESCR_SELECT(cccr, ev->escr_select);
|
||||
if (stag == 0) {
|
||||
if (stag == 0)
|
||||
CCCR_SET_PMI_OVF_0(cccr);
|
||||
} else {
|
||||
else
|
||||
CCCR_SET_PMI_OVF_1(cccr);
|
||||
}
|
||||
CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
printk(KERN_ERR
|
||||
printk(KERN_ERR
|
||||
"oprofile: P4 event code 0x%lx no binding, stag %d ctr %d\n",
|
||||
counter_config[ctr].event, stag, ctr);
|
||||
}
|
||||
|
|
@ -559,14 +557,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
|
|||
stag = get_stagger();
|
||||
|
||||
rdmsr(MSR_IA32_MISC_ENABLE, low, high);
|
||||
if (! MISC_PMC_ENABLED_P(low)) {
|
||||
if (!MISC_PMC_ENABLED_P(low)) {
|
||||
printk(KERN_ERR "oprofile: P4 PMC not available\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* clear the cccrs we will use */
|
||||
for (i = 0 ; i < num_counters ; i++) {
|
||||
if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
|
||||
if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
|
||||
continue;
|
||||
rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
|
||||
CCCR_CLEAR(low);
|
||||
|
|
@ -576,14 +574,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
|
|||
|
||||
/* clear all escrs (including those outside our concern) */
|
||||
for (i = num_counters; i < num_controls; i++) {
|
||||
if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
|
||||
if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
|
||||
continue;
|
||||
wrmsr(msrs->controls[i].addr, 0, 0);
|
||||
}
|
||||
|
||||
/* setup all counters */
|
||||
for (i = 0 ; i < num_counters ; ++i) {
|
||||
if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs,i))) {
|
||||
if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs, i))) {
|
||||
reset_value[i] = counter_config[i].count;
|
||||
pmc_setup_one_p4_counter(i);
|
||||
CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i));
|
||||
|
|
@ -603,11 +601,11 @@ static int p4_check_ctrs(struct pt_regs * const regs,
|
|||
stag = get_stagger();
|
||||
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
|
||||
if (!reset_value[i])
|
||||
|
||||
if (!reset_value[i])
|
||||
continue;
|
||||
|
||||
/*
|
||||
/*
|
||||
* there is some eccentricity in the hardware which
|
||||
* requires that we perform 2 extra corrections:
|
||||
*
|
||||
|
|
@ -616,24 +614,24 @@ static int p4_check_ctrs(struct pt_regs * const regs,
|
|||
*
|
||||
* - write the counter back twice to ensure it gets
|
||||
* updated properly.
|
||||
*
|
||||
*
|
||||
* the former seems to be related to extra NMIs happening
|
||||
* during the current NMI; the latter is reported as errata
|
||||
* N15 in intel doc 249199-029, pentium 4 specification
|
||||
* update, though their suggested work-around does not
|
||||
* appear to solve the problem.
|
||||
*/
|
||||
|
||||
|
||||
real = VIRT_CTR(stag, i);
|
||||
|
||||
CCCR_READ(low, high, real);
|
||||
CTR_READ(ctr, high, real);
|
||||
CTR_READ(ctr, high, real);
|
||||
if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
|
||||
oprofile_add_sample(regs, i);
|
||||
CTR_WRITE(reset_value[i], real);
|
||||
CTR_WRITE(reset_value[i], real);
|
||||
CCCR_CLEAR_OVF(low);
|
||||
CCCR_WRITE(low, high, real);
|
||||
CTR_WRITE(reset_value[i], real);
|
||||
CTR_WRITE(reset_value[i], real);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -683,15 +681,16 @@ static void p4_shutdown(struct op_msrs const * const msrs)
|
|||
int i;
|
||||
|
||||
for (i = 0 ; i < num_counters ; ++i) {
|
||||
if (CTR_IS_RESERVED(msrs,i))
|
||||
if (CTR_IS_RESERVED(msrs, i))
|
||||
release_perfctr_nmi(msrs->counters[i].addr);
|
||||
}
|
||||
/* some of the control registers are specially reserved in
|
||||
/*
|
||||
* some of the control registers are specially reserved in
|
||||
* conjunction with the counter registers (hence the starting offset).
|
||||
* This saves a few bits.
|
||||
*/
|
||||
for (i = num_counters ; i < num_controls ; ++i) {
|
||||
if (CTRL_IS_RESERVED(msrs,i))
|
||||
if (CTRL_IS_RESERVED(msrs, i))
|
||||
release_evntsel_nmi(msrs->controls[i].addr);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue