watchdog: Intel SCU Watchdog Timer Driver for Moorestown and Medfield platforms.
This submission includes:
- Fix to intel_scu_write() to start watchdog timer the on the
first write, and refresh on subsequent writes.
This enables Open, write, write, ... usage model.
- Moves boot parameter checks from intel_scu_open() to
intel_scu_watchdog_init(), so driver init will fail if these
parameters are out of bounds.
- Adds check for whether process waiting in wait_event_interruptible()
received a signal while it was waiting.
- Other small error handling changes.
Removed the read() method for now as that wass a non-standard behaviour.
Signed-off-by: Donald Johnson <donald.k.johnson@intel.com>
Signed-off-by: Shuduo Sang <shuduo.sang@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Donald Johnson
Wim Van Sebroeck
parent
742e4b6308
commit
57539c1cf9
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@ -533,6 +533,16 @@ config I6300ESB_WDT
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To compile this driver as a module, choose M here: the
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module will be called i6300esb.
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config INTEL_SCU_WATCHDOG
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bool "Intel SCU Watchdog for Mobile Platforms"
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depends on WATCHDOG
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depends on INTEL_SCU_IPC
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---help---
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Hardware driver for the watchdog time built into the Intel SCU
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for Intel Mobile Platforms.
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To compile this driver as a module, choose M here.
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config ITCO_WDT
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tristate "Intel TCO Timer/Watchdog"
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depends on (X86 || IA64) && PCI
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@ -102,6 +102,7 @@ obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
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obj-$(CONFIG_W83977F_WDT) += w83977f_wdt.o
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obj-$(CONFIG_MACHZ_WDT) += machzwd.o
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obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o
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obj-$(CONFIG_INTEL_SCU_WATCHDOG) += intel_scu_watchdog.o
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# M32R Architecture
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@ -0,0 +1,572 @@
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/*
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* Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
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* for Intel part #(s):
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* - AF82MP20 PCH
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*
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* Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General
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* Public License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write to the Free
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* Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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* The full GNU General Public License is included in this
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* distribution in the file called COPYING.
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*
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*/
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#include <linux/compiler.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/fs.h>
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#include <linux/notifier.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/jiffies.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/sfi.h>
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#include <linux/types.h>
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#include <asm/irq.h>
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#include <asm/atomic.h>
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#include <asm/intel_scu_ipc.h>
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#include <asm/apb_timer.h>
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#include <asm/mrst.h>
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#include "intel_scu_watchdog.h"
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/* Bounds number of times we will retry loading time count */
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/* This retry is a work around for a silicon bug. */
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#define MAX_RETRY 16
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#define IPC_SET_WATCHDOG_TIMER 0xF8
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static int timer_margin = DEFAULT_SOFT_TO_HARD_MARGIN;
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module_param(timer_margin, int, 0);
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MODULE_PARM_DESC(timer_margin,
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"Watchdog timer margin"
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"Time between interrupt and resetting the system"
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"The range is from 1 to 160"
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"This is the time for all keep alives to arrive");
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static int timer_set = DEFAULT_TIME;
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module_param(timer_set, int, 0);
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MODULE_PARM_DESC(timer_set,
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"Default Watchdog timer setting"
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"Complete cycle time"
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"The range is from 1 to 170"
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"This is the time for all keep alives to arrive");
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/* After watchdog device is closed, check force_boot. If:
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* force_boot == 0, then force boot on next watchdog interrupt after close,
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* force_boot == 1, then force boot immediately when device is closed.
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*/
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static int force_boot;
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module_param(force_boot, int, 0);
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MODULE_PARM_DESC(force_boot,
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"A value of 1 means that the driver will reboot"
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"the system immediately if the /dev/watchdog device is closed"
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"A value of 0 means that when /dev/watchdog device is closed"
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"the watchdog timer will be refreshed for one more interval"
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"of length: timer_set. At the end of this interval, the"
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"watchdog timer will reset the system."
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);
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/* there is only one device in the system now; this can be made into
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* an array in the future if we have more than one device */
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static struct intel_scu_watchdog_dev watchdog_device;
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/* Forces restart, if force_reboot is set */
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static void watchdog_fire(void)
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{
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if (force_boot) {
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printk(KERN_CRIT PFX "Initiating system reboot.\n");
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emergency_restart();
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printk(KERN_CRIT PFX "Reboot didn't ?????\n");
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}
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else {
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printk(KERN_CRIT PFX "Immediate Reboot Disabled\n");
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printk(KERN_CRIT PFX
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"System will reset when watchdog timer times out!\n");
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}
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}
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static int check_timer_margin(int new_margin)
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{
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if ((new_margin < MIN_TIME_CYCLE) ||
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(new_margin > MAX_TIME - timer_set)) {
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pr_debug("Watchdog timer: value of new_margin %d is out of the range %d to %d\n",
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new_margin, MIN_TIME_CYCLE, MAX_TIME - timer_set);
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return -EINVAL;
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}
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return 0;
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}
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/*
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* IPC operations
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*/
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static int watchdog_set_ipc(int soft_threshold, int threshold)
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{
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u32 *ipc_wbuf;
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u8 cbuf[16] = { '\0' };
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int ipc_ret = 0;
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ipc_wbuf = (u32 *)&cbuf;
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ipc_wbuf[0] = soft_threshold;
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ipc_wbuf[1] = threshold;
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ipc_ret = intel_scu_ipc_command(
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IPC_SET_WATCHDOG_TIMER,
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0,
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ipc_wbuf,
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2,
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NULL,
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0);
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if (ipc_ret != 0)
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pr_err("Error setting SCU watchdog timer: %x\n", ipc_ret);
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return ipc_ret;
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};
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/*
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* Intel_SCU operations
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*/
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/* timer interrupt handler */
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static irqreturn_t watchdog_timer_interrupt(int irq, void *dev_id)
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{
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int int_status;
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int_status = ioread32(watchdog_device.timer_interrupt_status_addr);
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pr_debug("Watchdog timer: irq, int_status: %x\n", int_status);
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if (int_status != 0)
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return IRQ_NONE;
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/* has the timer been started? If not, then this is spurious */
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if (watchdog_device.timer_started == 0) {
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pr_debug("Watchdog timer: spurious interrupt received\n");
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return IRQ_HANDLED;
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}
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/* temporarily disable the timer */
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iowrite32(0x00000002, watchdog_device.timer_control_addr);
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/* set the timer to the threshold */
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iowrite32(watchdog_device.threshold,
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watchdog_device.timer_load_count_addr);
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/* allow the timer to run */
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iowrite32(0x00000003, watchdog_device.timer_control_addr);
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return IRQ_HANDLED;
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}
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static int intel_scu_keepalive(void)
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{
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/* read eoi register - clears interrupt */
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ioread32(watchdog_device.timer_clear_interrupt_addr);
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/* temporarily disable the timer */
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iowrite32(0x00000002, watchdog_device.timer_control_addr);
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/* set the timer to the soft_threshold */
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iowrite32(watchdog_device.soft_threshold,
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watchdog_device.timer_load_count_addr);
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/* allow the timer to run */
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iowrite32(0x00000003, watchdog_device.timer_control_addr);
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return 0;
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}
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static int intel_scu_stop(void)
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{
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iowrite32(0, watchdog_device.timer_control_addr);
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return 0;
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}
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static int intel_scu_set_heartbeat(u32 t)
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{
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int ipc_ret;
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int retry_count;
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u32 soft_value;
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u32 hw_pre_value;
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u32 hw_value;
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watchdog_device.timer_set = t;
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watchdog_device.threshold =
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timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
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watchdog_device.soft_threshold =
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(watchdog_device.timer_set - timer_margin)
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* watchdog_device.timer_tbl_ptr->freq_hz;
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pr_debug("Watchdog timer: set_heartbeat: timer freq is %d\n",
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watchdog_device.timer_tbl_ptr->freq_hz);
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pr_debug("Watchdog timer: set_heartbeat: timer_set is %x (hex)\n",
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watchdog_device.timer_set);
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pr_debug("Watchdog timer: set_hearbeat: timer_margin is %x (hex)\n",
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timer_margin);
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pr_debug("Watchdog timer: set_heartbeat: threshold is %x (hex)\n",
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watchdog_device.threshold);
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pr_debug("Watchdog timer: set_heartbeat: soft_threshold is %x (hex)\n",
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watchdog_device.soft_threshold);
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/* Adjust thresholds by FREQ_ADJUSTMENT factor, to make the */
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/* watchdog timing come out right. */
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watchdog_device.threshold =
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watchdog_device.threshold / FREQ_ADJUSTMENT;
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watchdog_device.soft_threshold =
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watchdog_device.soft_threshold / FREQ_ADJUSTMENT;
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/* temporarily disable the timer */
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iowrite32(0x00000002, watchdog_device.timer_control_addr);
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/* send the threshold and soft_threshold via IPC to the processor */
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ipc_ret = watchdog_set_ipc(watchdog_device.soft_threshold,
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watchdog_device.threshold);
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if (ipc_ret != 0) {
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/* Make sure the watchdog timer is stopped */
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intel_scu_stop();
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return ipc_ret;
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}
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/* Soft Threshold set loop. Early versions of silicon did */
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/* not always set this count correctly. This loop checks */
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/* the value and retries if it was not set correctly. */
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retry_count = 0;
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soft_value = watchdog_device.soft_threshold & 0xFFFF0000;
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do {
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/* Make sure timer is stopped */
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intel_scu_stop();
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if (MAX_RETRY < retry_count++) {
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/* Unable to set timer value */
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pr_err("Watchdog timer: Unable to set timer\n");
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return -ENODEV;
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}
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/* set the timer to the soft threshold */
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iowrite32(watchdog_device.soft_threshold,
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watchdog_device.timer_load_count_addr);
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/* read count value before starting timer */
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hw_pre_value = ioread32(watchdog_device.timer_load_count_addr);
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hw_pre_value = hw_pre_value & 0xFFFF0000;
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/* Start the timer */
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iowrite32(0x00000003, watchdog_device.timer_control_addr);
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/* read the value the time loaded into its count reg */
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hw_value = ioread32(watchdog_device.timer_load_count_addr);
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hw_value = hw_value & 0xFFFF0000;
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} while (soft_value != hw_value);
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watchdog_device.timer_started = 1;
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return 0;
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}
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/*
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* /dev/watchdog handling
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*/
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static int intel_scu_open(struct inode *inode, struct file *file)
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{
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/* Set flag to indicate that watchdog device is open */
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if (test_and_set_bit(0, &watchdog_device.driver_open))
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return -EBUSY;
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/* Check for reopen of driver. Reopens are not allowed */
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if (watchdog_device.driver_closed)
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return -EPERM;
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return nonseekable_open(inode, file);
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}
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static int intel_scu_release(struct inode *inode, struct file *file)
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{
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/*
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* This watchdog should not be closed, after the timer
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* is started with the WDIPC_SETTIMEOUT ioctl
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* If force_boot is set watchdog_fire() will cause an
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* immediate reset. If force_boot is not set, the watchdog
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* timer is refreshed for one more interval. At the end
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* of that interval, the watchdog timer will reset the system.
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*/
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if (!test_and_clear_bit(0, &watchdog_device.driver_open)) {
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pr_debug("Watchdog timer: intel_scu_release, without open\n");
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return -ENOTTY;
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}
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if (!watchdog_device.timer_started) {
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/* Just close, since timer has not been started */
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pr_debug("Watchdog timer: closed, without starting timer\n");
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return 0;
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}
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printk(KERN_CRIT PFX
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"Unexpected close of /dev/watchdog!\n");
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/* Since the timer was started, prevent future reopens */
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watchdog_device.driver_closed = 1;
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/* Refresh the timer for one more interval */
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intel_scu_keepalive();
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/* Reboot system (if force_boot is set) */
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watchdog_fire();
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/* We should only reach this point if force_boot is not set */
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return 0;
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}
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static ssize_t intel_scu_write(struct file *file,
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char const *data,
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size_t len,
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loff_t *ppos)
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{
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if (watchdog_device.timer_started)
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/* Watchdog already started, keep it alive */
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intel_scu_keepalive();
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else
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/* Start watchdog with timer value set by init */
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intel_scu_set_heartbeat(watchdog_device.timer_set);
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return len;
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}
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static long intel_scu_ioctl(struct file *file,
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unsigned int cmd,
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unsigned long arg)
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{
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void __user *argp = (void __user *)arg;
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u32 __user *p = argp;
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u32 new_margin;
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static const struct watchdog_info ident = {
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.options = WDIOF_SETTIMEOUT
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| WDIOF_KEEPALIVEPING,
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.firmware_version = 0, /* @todo Get from SCU via
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ipc_get_scu_fw_version()? */
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.identity = "Intel_SCU IOH Watchdog" /* len < 32 */
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};
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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return copy_to_user(argp,
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&ident,
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sizeof(ident)) ? -EFAULT : 0;
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case WDIOC_GETSTATUS:
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case WDIOC_GETBOOTSTATUS:
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return put_user(0, p);
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case WDIOC_KEEPALIVE:
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intel_scu_keepalive();
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return 0;
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case WDIOC_SETTIMEOUT:
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if (get_user(new_margin, p))
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return -EFAULT;
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if (check_timer_margin(new_margin))
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return -EINVAL;
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if (intel_scu_set_heartbeat(new_margin))
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return -EINVAL;
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return 0;
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case WDIOC_GETTIMEOUT:
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return put_user(watchdog_device.soft_threshold, p);
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default:
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return -ENOTTY;
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}
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}
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/*
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* Notifier for system down
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*/
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static int intel_scu_notify_sys(struct notifier_block *this,
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unsigned long code,
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void *another_unused)
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{
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if (code == SYS_DOWN || code == SYS_HALT)
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/* Turn off the watchdog timer. */
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intel_scu_stop();
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return NOTIFY_DONE;
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}
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/*
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* Kernel Interfaces
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*/
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static const struct file_operations intel_scu_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = intel_scu_write,
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.unlocked_ioctl = intel_scu_ioctl,
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.open = intel_scu_open,
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.release = intel_scu_release,
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};
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static int __init intel_scu_watchdog_init(void)
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{
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int ret;
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u32 __iomem *tmp_addr;
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/*
|
||||
* We don't really need to check this as the SFI timer get will fail
|
||||
* but if we do so we can exit with a clearer reason and no noise.
|
||||
*
|
||||
* If it isn't an intel MID device then it doesn't have this watchdog
|
||||
*/
|
||||
if (!mrst_identify_cpu())
|
||||
return -ENODEV;
|
||||
|
||||
/* Check boot parameters to verify that their initial values */
|
||||
/* are in range. */
|
||||
/* Check value of timer_set boot parameter */
|
||||
if ((timer_set < MIN_TIME_CYCLE) ||
|
||||
(timer_set > MAX_TIME - MIN_TIME_CYCLE)) {
|
||||
pr_err("Watchdog timer: value of timer_set %x (hex) "
|
||||
"is out of range from %x to %x (hex)\n",
|
||||
timer_set, MIN_TIME_CYCLE, MAX_TIME - MIN_TIME_CYCLE);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Check value of timer_margin boot parameter */
|
||||
if (check_timer_margin(timer_margin))
|
||||
return -EINVAL;
|
||||
|
||||
watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);
|
||||
|
||||
if (watchdog_device.timer_tbl_ptr == NULL) {
|
||||
pr_debug("Watchdog timer - Intel SCU watchdog: timer is not available\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
/* make sure the timer exists */
|
||||
if (watchdog_device.timer_tbl_ptr->phys_addr == 0) {
|
||||
pr_debug("Watchdog timer - Intel SCU watchdog - timer %d does not have valid physical memory\n",
|
||||
sfi_mtimer_num);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (watchdog_device.timer_tbl_ptr->irq == 0) {
|
||||
pr_debug("Watchdog timer: timer %d invalid irq\n",
|
||||
sfi_mtimer_num);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
tmp_addr = ioremap_nocache(watchdog_device.timer_tbl_ptr->phys_addr,
|
||||
20);
|
||||
|
||||
if (tmp_addr == NULL) {
|
||||
pr_debug("Watchdog timer: timer unable to ioremap\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
watchdog_device.timer_load_count_addr = tmp_addr++;
|
||||
watchdog_device.timer_current_value_addr = tmp_addr++;
|
||||
watchdog_device.timer_control_addr = tmp_addr++;
|
||||
watchdog_device.timer_clear_interrupt_addr = tmp_addr++;
|
||||
watchdog_device.timer_interrupt_status_addr = tmp_addr++;
|
||||
|
||||
/* Set the default time values in device structure */
|
||||
|
||||
watchdog_device.timer_set = timer_set;
|
||||
watchdog_device.threshold =
|
||||
timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
|
||||
watchdog_device.soft_threshold =
|
||||
(watchdog_device.timer_set - timer_margin)
|
||||
* watchdog_device.timer_tbl_ptr->freq_hz;
|
||||
|
||||
|
||||
watchdog_device.intel_scu_notifier.notifier_call =
|
||||
intel_scu_notify_sys;
|
||||
|
||||
ret = register_reboot_notifier(&watchdog_device.intel_scu_notifier);
|
||||
if (ret) {
|
||||
pr_err("Watchdog timer: cannot register notifier %d)\n", ret);
|
||||
goto register_reboot_error;
|
||||
}
|
||||
|
||||
watchdog_device.miscdev.minor = WATCHDOG_MINOR;
|
||||
watchdog_device.miscdev.name = "watchdog";
|
||||
watchdog_device.miscdev.fops = &intel_scu_fops;
|
||||
|
||||
ret = misc_register(&watchdog_device.miscdev);
|
||||
if (ret) {
|
||||
pr_err("Watchdog timer: cannot register miscdev %d err =%d\n",
|
||||
WATCHDOG_MINOR, ret);
|
||||
goto misc_register_error;
|
||||
}
|
||||
|
||||
ret = request_irq((unsigned int)watchdog_device.timer_tbl_ptr->irq,
|
||||
watchdog_timer_interrupt,
|
||||
IRQF_SHARED, "watchdog",
|
||||
&watchdog_device.timer_load_count_addr);
|
||||
if (ret) {
|
||||
pr_err("Watchdog timer: error requesting irq %d\n", ret);
|
||||
goto request_irq_error;
|
||||
}
|
||||
/* Make sure timer is disabled before returning */
|
||||
intel_scu_stop();
|
||||
return 0;
|
||||
|
||||
/* error cleanup */
|
||||
|
||||
request_irq_error:
|
||||
misc_deregister(&watchdog_device.miscdev);
|
||||
misc_register_error:
|
||||
unregister_reboot_notifier(&watchdog_device.intel_scu_notifier);
|
||||
register_reboot_error:
|
||||
intel_scu_stop();
|
||||
iounmap(watchdog_device.timer_load_count_addr);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit intel_scu_watchdog_exit(void)
|
||||
{
|
||||
|
||||
misc_deregister(&watchdog_device.miscdev);
|
||||
unregister_reboot_notifier(&watchdog_device.intel_scu_notifier);
|
||||
/* disable the timer */
|
||||
iowrite32(0x00000002, watchdog_device.timer_control_addr);
|
||||
iounmap(watchdog_device.timer_load_count_addr);
|
||||
}
|
||||
|
||||
late_initcall(intel_scu_watchdog_init);
|
||||
module_exit(intel_scu_watchdog_exit);
|
||||
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
MODULE_DESCRIPTION("Intel SCU Watchdog Device Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
MODULE_VERSION(WDT_VER);
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
|
||||
* for Intel part #(s):
|
||||
* - AF82MP20 PCH
|
||||
*
|
||||
* Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of version 2 of the GNU General
|
||||
* Public License as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be
|
||||
* useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. See the GNU General Public License for more details.
|
||||
* You should have received a copy of the GNU General Public
|
||||
* License along with this program; if not, write to the Free
|
||||
* Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
* The full GNU General Public License is included in this
|
||||
* distribution in the file called COPYING.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_SCU_WATCHDOG_H
|
||||
#define __INTEL_SCU_WATCHDOG_H
|
||||
|
||||
#define PFX "Intel_SCU: "
|
||||
#define WDT_VER "0.3"
|
||||
|
||||
/* minimum time between interrupts */
|
||||
#define MIN_TIME_CYCLE 1
|
||||
|
||||
/* Time from warning to reboot is 2 seconds */
|
||||
#define DEFAULT_SOFT_TO_HARD_MARGIN 2
|
||||
|
||||
#define MAX_TIME 170
|
||||
|
||||
#define DEFAULT_TIME 5
|
||||
|
||||
#define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
|
||||
|
||||
/* Ajustment to clock tick frequency to make timing come out right */
|
||||
#define FREQ_ADJUSTMENT 8
|
||||
|
||||
struct intel_scu_watchdog_dev {
|
||||
ulong driver_open;
|
||||
ulong driver_closed;
|
||||
u32 timer_started;
|
||||
u32 timer_set;
|
||||
u32 threshold;
|
||||
u32 soft_threshold;
|
||||
u32 __iomem *timer_load_count_addr;
|
||||
u32 __iomem *timer_current_value_addr;
|
||||
u32 __iomem *timer_control_addr;
|
||||
u32 __iomem *timer_clear_interrupt_addr;
|
||||
u32 __iomem *timer_interrupt_status_addr;
|
||||
struct sfi_timer_table_entry *timer_tbl_ptr;
|
||||
struct notifier_block intel_scu_notifier;
|
||||
struct miscdevice miscdev;
|
||||
};
|
||||
|
||||
extern int sfi_mtimer_num;
|
||||
|
||||
/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
|
||||
#endif /* __INTEL_SCU_WATCHDOG_H */
|
||||
Loading…
Reference in New Issue