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[OMAP850] IRQ related changes 

IRQ related changes.

Signed-off-by: Zebediah C. McClure <zmc@lurian.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Zebediah C. McClure 2009-03-23 18:07:45 -07:00 committed by Tony Lindgren
parent 557096fe28
commit 59185eeeaa
2 changed files with 99 additions and 3 deletions
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19
arch/arm/mach-omap1/irq.c
View File

@ -145,6 +145,14 @@ static struct omap_irq_bank omap730_irq_banks[] = {
};
#endif
#ifdef CONFIG_ARCH_OMAP850
static struct omap_irq_bank omap850_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
};
#endif
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_irq_bank omap1510_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
@ -184,6 +192,12 @@ void __init omap_init_irq(void)
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP850
if (cpu_is_omap850()) {
irq_banks = omap850_irq_banks;
irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
@ -214,9 +228,8 @@ void __init omap_init_irq(void)
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
/* Enable interrupts in global mask */
if (cpu_is_omap730()) {
if (cpu_is_omap7xx())
irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
}
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
@ -236,6 +249,8 @@ void __init omap_init_irq(void)
if (cpu_is_omap730())
omap_unmask_irq(INT_730_IH2_IRQ);
else if (cpu_is_omap850())
omap_unmask_irq(INT_850_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())

83
arch/arm/plat-omap/include/mach/irqs.h
View File

@ -104,6 +104,29 @@
#define INT_730_GPIO_BANK6 18
#define INT_730_SPGIO_WR 29
/*
* OMAP-850 specific IRQ numbers for interrupt handler 1
*/
#define INT_850_IH2_FIQ 0
#define INT_850_IH2_IRQ 1
#define INT_850_USB_NON_ISO 2
#define INT_850_USB_ISO 3
#define INT_850_ICR 4
#define INT_850_EAC 5
#define INT_850_GPIO_BANK1 6
#define INT_850_GPIO_BANK2 7
#define INT_850_GPIO_BANK3 8
#define INT_850_McBSP2TX 10
#define INT_850_McBSP2RX 11
#define INT_850_McBSP2RX_OVF 12
#define INT_850_LCD_LINE 14
#define INT_850_GSM_PROTECT 15
#define INT_850_TIMER3 16
#define INT_850_GPIO_BANK5 17
#define INT_850_GPIO_BANK6 18
#define INT_850_SPGIO_WR 29
/*
* IRQ numbers for interrupt handler 2
*
@ -237,6 +260,64 @@
#define INT_730_DMA_CH15 (62 + IH2_BASE)
#define INT_730_NAND (63 + IH2_BASE)
/*
* OMAP-850 specific IRQ numbers for interrupt handler 2
*/
#define INT_850_HW_ERRORS (0 + IH2_BASE)
#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE)
#define INT_850_CFCD (2 + IH2_BASE)
#define INT_850_CFIREQ (3 + IH2_BASE)
#define INT_850_I2C (4 + IH2_BASE)
#define INT_850_PCC (5 + IH2_BASE)
#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE)
#define INT_850_SPI_100K_1 (7 + IH2_BASE)
#define INT_850_SYREN_SPI (8 + IH2_BASE)
#define INT_850_VLYNQ (9 + IH2_BASE)
#define INT_850_GPIO_BANK4 (10 + IH2_BASE)
#define INT_850_McBSP1TX (11 + IH2_BASE)
#define INT_850_McBSP1RX (12 + IH2_BASE)
#define INT_850_McBSP1RX_OF (13 + IH2_BASE)
#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_850_UART_MODEM_1 (15 + IH2_BASE)
#define INT_850_MCSI (16 + IH2_BASE)
#define INT_850_uWireTX (17 + IH2_BASE)
#define INT_850_uWireRX (18 + IH2_BASE)
#define INT_850_SMC_CD (19 + IH2_BASE)
#define INT_850_SMC_IREQ (20 + IH2_BASE)
#define INT_850_HDQ_1WIRE (21 + IH2_BASE)
#define INT_850_TIMER32K (22 + IH2_BASE)
#define INT_850_MMC_SDIO (23 + IH2_BASE)
#define INT_850_UPLD (24 + IH2_BASE)
#define INT_850_USB_HHC_1 (27 + IH2_BASE)
#define INT_850_USB_HHC_2 (28 + IH2_BASE)
#define INT_850_USB_GENI (29 + IH2_BASE)
#define INT_850_USB_OTG (30 + IH2_BASE)
#define INT_850_CAMERA_IF (31 + IH2_BASE)
#define INT_850_RNG (32 + IH2_BASE)
#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_850_DBB_RF_EN (34 + IH2_BASE)
#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE)
#define INT_850_SHA1_MD5 (36 + IH2_BASE)
#define INT_850_SPI_100K_2 (37 + IH2_BASE)
#define INT_850_RNG_IDLE (38 + IH2_BASE)
#define INT_850_MPUIO (39 + IH2_BASE)
#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_850_LLPC_OE_RISING (42 + IH2_BASE)
#define INT_850_LLPC_VSYNC (43 + IH2_BASE)
#define INT_850_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_850_DMA_CH6 (53 + IH2_BASE)
#define INT_850_DMA_CH7 (54 + IH2_BASE)
#define INT_850_DMA_CH8 (55 + IH2_BASE)
#define INT_850_DMA_CH9 (56 + IH2_BASE)
#define INT_850_DMA_CH10 (57 + IH2_BASE)
#define INT_850_DMA_CH11 (58 + IH2_BASE)
#define INT_850_DMA_CH12 (59 + IH2_BASE)
#define INT_850_DMA_CH13 (60 + IH2_BASE)
#define INT_850_DMA_CH14 (61 + IH2_BASE)
#define INT_850_DMA_CH15 (62 + IH2_BASE)
#define INT_850_NAND (63 + IH2_BASE)
#define INT_24XX_SYS_NIRQ 7
#define INT_24XX_SDMA_IRQ0 12
#define INT_24XX_SDMA_IRQ1 13
@ -341,7 +422,7 @@
#define INT_34XX_BENCH_MPU_EMUL 3
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192
#define IH_GPIO_BASE (128 + IH2_BASE)