[POWERPC] Allow drivers to map individual 4k pages to userspace
Some drivers have resources that they want to be able to map into userspace that are 4k in size. On a kernel configured with 64k pages we currently end up mapping the 4k we want plus another 60k of physical address space, which could contain anything. This can introduce security problems, for example in the case of an infiniband adaptor where the other 60k could contain registers that some other program is using for its communications. This patch adds a new function, remap_4k_pfn, which drivers can use to map a single 4k page to userspace regardless of whether the kernel is using a 4k or a 64k page size. Like remap_pfn_range, it would typically be called in a driver's mmap function. It only maps a single 4k page, which on a 64k page kernel appears replicated 16 times throughout a 64k page. On a 4k page kernel it reduces to a call to remap_pfn_range. The way this works on a 64k kernel is that a new bit, _PAGE_4K_PFN, gets set on the linux PTE. This alters the way that __hash_page_4K computes the real address to put in the HPTE. The RPN field of the linux PTE becomes the 4k RPN directly rather than being interpreted as a 64k RPN. Since the RPN field is 32 bits, this means that physical addresses being mapped with remap_4k_pfn have to be below 2^44, i.e. 0x100000000000. The patch also factors out the code in arch/powerpc/mm/hash_utils_64.c that deals with demoting a process to use 4k pages into one function that gets called in the various different places where we need to do that. There were some discrepancies between exactly what was done in the various places, such as a call to spu_flush_all_slbs in one case but not in others. Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -445,9 +445,12 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
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htab_insert_pte:
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htab_insert_pte:
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/* real page number in r5, PTE RPN value + index */
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/* real page number in r5, PTE RPN value + index */
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rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
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andis. r0,r31,_PAGE_4K_PFN@h
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srdi r5,r31,PTE_RPN_SHIFT
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bne- htab_special_pfn
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sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
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sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
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add r5,r5,r25
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add r5,r5,r25
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htab_special_pfn:
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sldi r5,r5,HW_PAGE_SHIFT
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sldi r5,r5,HW_PAGE_SHIFT
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/* Calculate primary group hash */
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/* Calculate primary group hash */
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@ -573,6 +573,27 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
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return pp;
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return pp;
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}
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}
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/*
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* Demote a segment to using 4k pages.
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* For now this makes the whole process use 4k pages.
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*/
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void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
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{
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#ifdef CONFIG_PPC_64K_PAGES
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if (mm->context.user_psize == MMU_PAGE_4K)
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return;
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mm->context.user_psize = MMU_PAGE_4K;
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mm->context.sllp = SLB_VSID_USER | mmu_psize_defs[MMU_PAGE_4K].sllp;
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get_paca()->context = mm->context;
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slb_flush_and_rebolt();
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#ifdef CONFIG_SPE_BASE
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spu_flush_all_slbs(mm);
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#endif
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#endif
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}
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EXPORT_SYMBOL_GPL(demote_segment_4k);
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/* Result code is:
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/* Result code is:
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* 0 - handled
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* 0 - handled
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* 1 - normal page fault
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* 1 - normal page fault
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@ -665,15 +686,19 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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#ifndef CONFIG_PPC_64K_PAGES
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#ifndef CONFIG_PPC_64K_PAGES
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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#else
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#else
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/* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
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if (pte_val(*ptep) & _PAGE_4K_PFN) {
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demote_segment_4k(mm, ea);
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psize = MMU_PAGE_4K;
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}
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if (mmu_ci_restrictions) {
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if (mmu_ci_restrictions) {
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/* If this PTE is non-cacheable, switch to 4k */
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/* If this PTE is non-cacheable, switch to 4k */
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if (psize == MMU_PAGE_64K &&
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if (psize == MMU_PAGE_64K &&
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(pte_val(*ptep) & _PAGE_NO_CACHE)) {
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(pte_val(*ptep) & _PAGE_NO_CACHE)) {
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if (user_region) {
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if (user_region) {
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demote_segment_4k(mm, ea);
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psize = MMU_PAGE_4K;
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psize = MMU_PAGE_4K;
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mm->context.user_psize = MMU_PAGE_4K;
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mm->context.sllp = SLB_VSID_USER |
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mmu_psize_defs[MMU_PAGE_4K].sllp;
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} else if (ea < VMALLOC_END) {
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} else if (ea < VMALLOC_END) {
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/*
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/*
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* some driver did a non-cacheable mapping
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* some driver did a non-cacheable mapping
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@ -756,16 +781,8 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
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if (mmu_ci_restrictions) {
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if (mmu_ci_restrictions) {
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/* If this PTE is non-cacheable, switch to 4k */
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/* If this PTE is non-cacheable, switch to 4k */
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if (mm->context.user_psize == MMU_PAGE_64K &&
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if (mm->context.user_psize == MMU_PAGE_64K &&
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(pte_val(*ptep) & _PAGE_NO_CACHE)) {
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(pte_val(*ptep) & _PAGE_NO_CACHE))
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mm->context.user_psize = MMU_PAGE_4K;
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demote_segment_4k(mm, ea);
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mm->context.sllp = SLB_VSID_USER |
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mmu_psize_defs[MMU_PAGE_4K].sllp;
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get_paca()->context = mm->context;
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slb_flush_and_rebolt();
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#ifdef CONFIG_SPE_BASE
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spu_flush_all_slbs(mm);
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#endif
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}
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}
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}
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if (mm->context.user_psize == MMU_PAGE_64K)
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if (mm->context.user_psize == MMU_PAGE_64K)
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__hash_page_64K(ea, access, vsid, ptep, trap, local);
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__hash_page_64K(ea, access, vsid, ptep, trap, local);
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@ -97,3 +97,6 @@
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#define pud_ERROR(e) \
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#define pud_ERROR(e) \
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printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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@ -35,6 +35,7 @@
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#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
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#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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@ -93,6 +94,10 @@
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#define pte_pagesize_index(pte) \
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#define pte_pagesize_index(pte) \
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(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
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__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PGTABLE_64K_H */
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#endif /* _ASM_POWERPC_PGTABLE_64K_H */
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