x86/oprofile: Fix cast of counter value
When casting the counter value to a 64 bit value in 32 bit mode, sign extension may lead to broken counter values. This patch fixes this by casting to (u64) instead of (s64). Signed-off-by: Robert Richter <robert.richter@amd.com>
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@ -111,7 +111,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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if (counter_config[i].enabled && msrs->counters[i].addr) {
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reset_value[i] = counter_config[i].count;
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wrmsrl(msrs->counters[i].addr,
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-(s64)counter_config[i].count);
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-(u64)counter_config[i].count);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[i]);
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@ -237,7 +237,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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if (val & OP_CTR_OVERFLOW)
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continue;
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oprofile_add_sample(regs, i);
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wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[i]);
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}
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op_amd_handle_ibs(regs, msrs);
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@ -580,7 +580,7 @@ static void p4_setup_ctrs(struct op_x86_model_spec const *model,
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reset_value[i] = counter_config[i].count;
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pmc_setup_one_p4_counter(i);
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wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address,
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-(s64)counter_config[i].count);
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-(u64)counter_config[i].count);
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} else {
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reset_value[i] = 0;
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}
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@ -625,11 +625,11 @@ static int p4_check_ctrs(struct pt_regs * const regs,
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if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) {
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oprofile_add_sample(regs, i);
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wrmsrl(p4_counters[real].counter_address,
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-(s64)reset_value[i]);
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-(u64)reset_value[i]);
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CCCR_CLEAR_OVF(low);
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wrmsr(p4_counters[real].cccr_address, low, high);
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wrmsrl(p4_counters[real].counter_address,
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-(s64)reset_value[i]);
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-(u64)reset_value[i]);
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}
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}
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