MIPS: Set io_map_base for several PCI bridges lacking it
Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr <tbm@cyrius.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -247,6 +247,8 @@ void __init mips_pcibios_init(void)
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iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
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ioport_resource.end = controller->io_resource->end;
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controller->io_map_base = mips_io_port_base;
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register_pci_controller(controller);
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}
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@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
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static struct pci_controller pnx8550_controller = {
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.pci_ops = &pnx8550_pci_ops,
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.io_map_base = PNX8550_PORT_BASE,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource,
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};
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@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
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PNX8550_GLB2_ENAB_INTA_O = 0;
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/* IO/MEM resources. */
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set_io_port_base(KSEG1);
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set_io_port_base(PNX8550_PORT_BASE);
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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iomem_resource.start = 0;
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@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = {
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.pci_ops = &msp_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0,
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.io_map_base = MSP_PCI_IOSPACE_BASE,
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.io_resource = &pci_io_resource,
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.io_offset = 0
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};
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@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void)
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panic(ioremap_failed);
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set_io_port_base(io_v_base);
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py_controller.io_map_base = io_v_base;
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TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
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ioport_resource.end = TITAN_IO_SIZE - 1;
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