[PATCH] USB: EHCI updates mostly whitespace cleanups
This cleans up the recent updates to EHCI PCI support:
- Gets rid of checks for "is this a PCI device", they're no
longer needed since this is now all PCI-only code.
- Reduce log spamming: MWI is only interesting in the atypical
case that it can actually be used.
- Whitespace cleanup, as appropriate for a new file with no
other pending patches.
So other than that minor logging change, no functional updates.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
David Brownell
Linus Torvalds
parent
f03c17fc9a
commit
abcc944806
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@ -27,7 +27,7 @@
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/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
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* off the controller (maybe it can boot from highspeed USB disks).
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*/
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static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
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static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
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{
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struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
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@ -48,7 +48,7 @@ static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
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where, cap);
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// some BIOS versions seem buggy...
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// return 1;
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ehci_warn (ehci, "continuing after BIOS bug...\n");
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ehci_warn(ehci, "continuing after BIOS bug...\n");
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/* disable all SMIs, and clear "BIOS owns" flag */
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pci_write_config_dword(pdev, where + 4, 0);
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pci_write_config_byte(pdev, where + 2, 0);
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@ -59,95 +59,93 @@ static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
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}
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/* called by khubd or root hub init threads */
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static int ehci_pci_reset (struct usb_hcd *hcd)
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static int ehci_pci_reset(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u32 temp;
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unsigned count = 256/4;
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spin_lock_init (&ehci->lock);
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
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dbg_hcs_params (ehci, "reset");
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dbg_hcc_params (ehci, "reset");
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ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = readl (&ehci->caps->hcs_params);
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ehci->hcs_params = readl(&ehci->caps->hcs_params);
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/* NOTE: only the parts below this line are PCI-specific */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
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ehci->is_tdi_rh_tt = 1;
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tdi_reset (ehci);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info (ehci, "ignoring AMD8111 (errata)\n");
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return -EIO;
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_31BIT_MASK) < 0)
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ehci_warn (ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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}
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
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ehci->is_tdi_rh_tt = 1;
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tdi_reset(ehci);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info(ehci, "ignoring AMD8111 (errata)\n");
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return -EIO;
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_31BIT_MASK) < 0)
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ehci_warn(ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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}
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break;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability (pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = readl (&ehci->debug->control);
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ehci_info (ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = readl(&ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
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} else
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temp = 0;
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temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
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/* EHCI 0.96 and later may have "extended capabilities" */
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while (temp && count--) {
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u32 cap;
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pci_read_config_dword (to_pci_dev(hcd->self.controller),
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pci_read_config_dword(to_pci_dev(hcd->self.controller),
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temp, &cap);
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ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
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ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff */
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if (bios_handoff (ehci, temp, cap) != 0)
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if (bios_handoff(ehci, temp, cap) != 0)
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return -EOPNOTSUPP;
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break;
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case 0: /* illegal reserved capability */
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ehci_warn (ehci, "illegal capability!\n");
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ehci_warn(ehci, "illegal capability!\n");
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cap = 0;
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/* FALLTHROUGH */
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default: /* unknown */
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@ -156,77 +154,69 @@ static int ehci_pci_reset (struct usb_hcd *hcd)
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temp = (cap >> 8) & 0xff;
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}
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if (!count) {
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ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
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ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
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return -EIO;
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}
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if (ehci_is_TDI(ehci))
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ehci_reset (ehci);
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ehci_reset(ehci);
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ehci_port_power (ehci, 0);
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ehci_port_power(ehci, 0);
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
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ehci_dbg (ehci, "bogus port configuration: "
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ehci_dbg(ehci, "bogus port configuration: "
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"cc=%d x pcc=%d < ports=%d\n",
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HCS_N_CC(ehci->hcs_params),
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HCS_N_PCC(ehci->hcs_params),
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HCS_N_PORTS(ehci->hcs_params));
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev;
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pdev = to_pci_dev(hcd->self.controller);
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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}
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/* force HC to halt state */
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return ehci_halt (ehci);
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return ehci_halt(ehci);
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}
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static int ehci_pci_start (struct usb_hcd *hcd)
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static int ehci_pci_start(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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int result = 0;
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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int result = 0;
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struct pci_dev *pdev;
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u16 port_wake;
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if (hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev;
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u16 port_wake;
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pdev = to_pci_dev(hcd->self.controller);
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pdev = to_pci_dev(hcd->self.controller);
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* port wake capability, reported by boot firmware */
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pci_read_config_word(pdev, 0x62, &port_wake);
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hcd->can_wakeup = (port_wake & 1) != 0;
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/* port wake capability, reported by boot firmware */
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pci_read_config_word(pdev, 0x62, &port_wake);
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hcd->can_wakeup = (port_wake & 1) != 0;
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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result = pci_set_mwi(pdev);
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if (!result)
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ehci_dbg(ehci, "MWI active\n");
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/* help hc dma work well with cachelines */
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result = pci_set_mwi(pdev);
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if (result)
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ehci_dbg(ehci, "unable to enable MWI - not fatal.\n");
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}
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return ehci_run (hcd);
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return ehci_run(hcd);
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}
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/* always called by thread; normally rmmod */
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static void ehci_pci_stop (struct usb_hcd *hcd)
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static void ehci_pci_stop(struct usb_hcd *hcd)
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{
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ehci_stop (hcd);
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ehci_stop(hcd);
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}
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/*-------------------------------------------------------------------------*/
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@ -242,12 +232,12 @@ static void ehci_pci_stop (struct usb_hcd *hcd)
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* Also they depend on separate root hub suspend/resume.
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*/
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static int ehci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
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static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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if (time_before (jiffies, ehci->next_statechange))
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msleep (10);
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if (time_before(jiffies, ehci->next_statechange))
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msleep(10);
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// could save FLADJ in case of Vaux power loss
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// ... we'd only use it to handle clock skew
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@ -255,30 +245,30 @@ static int ehci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
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return 0;
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}
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static int ehci_pci_resume (struct usb_hcd *hcd)
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static int ehci_pci_resume(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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unsigned port;
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struct usb_device *root = hcd->self.root_hub;
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int retval = -EINVAL;
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// maybe restore FLADJ
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if (time_before (jiffies, ehci->next_statechange))
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msleep (100);
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if (time_before(jiffies, ehci->next_statechange))
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msleep(100);
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/* If CF is clear, we lost PCI Vaux power and need to restart. */
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if (readl (&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
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if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
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goto restart;
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/* If any port is suspended (or owned by the companion),
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* we know we can/must resume the HC (and mustn't reset it).
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* We just defer that to the root hub code.
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*/
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for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
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for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
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u32 status;
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port--;
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status = readl (&ehci->regs->port_status [port]);
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status = readl(&ehci->regs->port_status [port]);
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if (!(status & PORT_POWER))
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continue;
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if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
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@ -289,35 +279,35 @@ static int ehci_pci_resume (struct usb_hcd *hcd)
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restart:
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ehci_dbg(ehci, "lost power, restarting\n");
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for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
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for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
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port--;
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if (!root->children [port])
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continue;
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usb_set_device_state (root->children[port],
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usb_set_device_state(root->children[port],
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USB_STATE_NOTATTACHED);
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}
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/* Else reset, to cope with power loss or flush-to-storage
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* style "resume" having let BIOS kick in during reboot.
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*/
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(void) ehci_halt (ehci);
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(void) ehci_reset (ehci);
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(void) ehci_pci_reset (hcd);
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(void) ehci_halt(ehci);
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(void) ehci_reset(ehci);
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(void) ehci_pci_reset(hcd);
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/* emptying the schedule aborts any urbs */
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spin_lock_irq (&ehci->lock);
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spin_lock_irq(&ehci->lock);
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if (ehci->reclaim)
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ehci->reclaim_ready = 1;
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ehci_work (ehci, NULL);
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spin_unlock_irq (&ehci->lock);
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ehci_work(ehci, NULL);
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spin_unlock_irq(&ehci->lock);
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/* restart; khubd will disconnect devices */
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retval = ehci_run (hcd);
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retval = ehci_run(hcd);
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/* here we "know" root ports should always stay powered;
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* but some controllers may lose all power.
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*/
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ehci_port_power (ehci, 1);
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ehci_port_power(ehci, 1);
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return retval;
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}
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@ -376,7 +366,7 @@ static const struct pci_device_id pci_ids [] = { {
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE (pci, pci_ids);
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ehci_pci_driver = {
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@ -392,22 +382,22 @@ static struct pci_driver ehci_pci_driver = {
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#endif
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};
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static int __init ehci_hcd_pci_init (void)
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static int __init ehci_hcd_pci_init(void)
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{
|
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if (usb_disabled())
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return -ENODEV;
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|
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pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
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pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
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hcd_name,
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sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
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||||
sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
|
||||
sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
|
||||
sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
|
||||
|
||||
return pci_register_driver (&ehci_pci_driver);
|
||||
return pci_register_driver(&ehci_pci_driver);
|
||||
}
|
||||
module_init (ehci_hcd_pci_init);
|
||||
module_init(ehci_hcd_pci_init);
|
||||
|
||||
static void __exit ehci_hcd_pci_cleanup (void)
|
||||
static void __exit ehci_hcd_pci_cleanup(void)
|
||||
{
|
||||
pci_unregister_driver (&ehci_pci_driver);
|
||||
pci_unregister_driver(&ehci_pci_driver);
|
||||
}
|
||||
module_exit (ehci_hcd_pci_cleanup);
|
||||
module_exit(ehci_hcd_pci_cleanup);
|
||||
|
|
|
|||
Loading…
Reference in New Issue