[ARM] 4989/1: [AT91] SAM9 ClockSource / ClockEvents
Update AT91SAM9/CAP9 PIT driver to use generic time and clockevent infrastructure: - Clocksource gives sub-microsecond timestamp precision, assuming memory is clocked at over 16 MHz. It's less than a 32 bit counter, unless it's is also generating IRQs. - Clockevent device supports periodic mode only; no oneshot support from this hardware. No IRQs generated unless it's the active clocksource. Later, another timer (probably from a TC module) can provide a oneshot clockevent device to get NO_HZ and High-Res-Timer behavior. This also updates the timekeeping to use the actual master clock rate on the system, instead of compile-time <asm/arch/timex.h> constants matching what Atmel's EK boards use. (Product boards may well differ!) Plus cleanup: rename "*_timer*" symbols to "*_pit*" (there are other timers, but only one PIT); shorter lines; remove needless CPP stuff; make several symbols static; etc. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
11aadac4f6
commit
ad48ce74f7
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@ -12,18 +12,28 @@ config ARCH_AT91RM9200
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config ARCH_AT91SAM9260
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bool "AT91SAM9260 or AT91SAM9XE"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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config ARCH_AT91SAM9261
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bool "AT91SAM9261"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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config ARCH_AT91SAM9263
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bool "AT91SAM9263"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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config ARCH_AT91SAM9RL
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bool "AT91SAM9RL"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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config ARCH_AT91CAP9
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bool "AT91CAP9"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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config ARCH_AT91X40
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bool "AT91x40"
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@ -1,23 +1,20 @@
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/*
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* linux/arch/arm/mach-at91/at91sam926x_time.c
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* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
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*
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* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
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* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
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* Converted to ClockSource/ClockEvents by David Brownell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/mach/time.h>
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#include <asm/arch/at91_pit.h>
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@ -26,85 +23,167 @@
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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static u32 pit_cycle; /* write-once */
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static u32 pit_cnt; /* access only w/system irq blocked */
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/*
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* Returns number of microseconds since last timer interrupt. Note that interrupts
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* will have been disabled by do_gettimeofday()
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* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
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* Clocksource: just a monotonic counter of MCK/16 cycles.
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* We don't care whether or not PIT irqs are enabled.
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*/
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static unsigned long at91sam926x_gettimeoffset(void)
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static cycle_t read_pit_clk(void)
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{
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unsigned long elapsed;
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unsigned long t = at91_sys_read(AT91_PIT_PIIR);
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unsigned long flags;
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u32 elapsed;
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u32 t;
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elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
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raw_local_irq_save(flags);
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elapsed = pit_cnt;
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t = at91_sys_read(AT91_PIT_PIIR);
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raw_local_irq_restore(flags);
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return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
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elapsed += PIT_PICNT(t) * pit_cycle;
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elapsed += PIT_CPIV(t);
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return elapsed;
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}
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static struct clocksource pit_clk = {
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.name = "pit",
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.rating = 175,
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.read = read_pit_clk,
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
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*/
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static void
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pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long flags;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* update clocksource counter, then enable the IRQ */
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raw_local_irq_save(flags);
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pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
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| AT91_PIT_PITIEN);
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raw_local_irq_restore(flags);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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BUG();
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/* FALLTHROUGH */
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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/* disable irq, leaving the clocksource active */
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at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device pit_clkevt = {
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.name = "pit",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 100,
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.cpumask = CPU_MASK_CPU0,
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.set_mode = pit_clkevt_mode,
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};
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
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static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
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{
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volatile long nr_ticks;
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if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
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/* Get number to ticks performed before interrupt and clear PIT interrupt */
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/* The PIT interrupt may be disabled, and is shared */
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if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
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&& (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
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unsigned nr_ticks;
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/* Get number of ticks performed before irq, and ack it */
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nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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do {
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timer_tick();
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pit_cnt += pit_cycle;
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pit_clkevt.event_handler(&pit_clkevt);
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nr_ticks--;
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} while (nr_ticks);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE; /* not handled */
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}
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return IRQ_NONE;
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}
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static struct irqaction at91sam926x_timer_irq = {
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static struct irqaction at91sam926x_pit_irq = {
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.name = "at91_tick",
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.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = at91sam926x_timer_interrupt
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.handler = at91sam926x_pit_interrupt
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};
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void at91sam926x_timer_reset(void)
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static void at91sam926x_pit_reset(void)
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{
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/* Disable timer */
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/* Disable timer and irqs */
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at91_sys_write(AT91_PIT_MR, 0);
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/* Clear any pending interrupts */
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(void) at91_sys_read(AT91_PIT_PIVR);
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
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cpu_relax();
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/* Set Period Interval timer and enable its interrupt */
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at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
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/* Start PIT but don't enable IRQ */
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at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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}
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/*
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* Set up timer interrupt.
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* Set up both clocksource and clockevent support.
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*/
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void __init at91sam926x_timer_init(void)
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static void __init at91sam926x_pit_init(void)
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{
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/* Initialize and enable the timer */
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at91sam926x_timer_reset();
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unsigned long pit_rate;
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unsigned bits;
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/* Make IRQs happen for the system timer. */
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setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
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pit_cycle = (pit_rate + HZ/2) / HZ;
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WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
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/* Initialize and enable the timer */
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at91sam926x_pit_reset();
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/*
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* Register clocksource. The high order bits of PIV are unused,
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* so this isn't a 32-bit counter unless we get clockevent irqs.
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*/
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pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
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bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
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pit_clk.mask = CLOCKSOURCE_MASK(bits);
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clocksource_register(&pit_clk);
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/* Set up irq handler */
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setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
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/* Set up and register clockevents */
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pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
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clockevents_register_device(&pit_clkevt);
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}
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#ifdef CONFIG_PM
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static void at91sam926x_timer_suspend(void)
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static void at91sam926x_pit_suspend(void)
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{
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/* Disable timer */
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at91_sys_write(AT91_PIT_MR, 0);
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}
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#else
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#define at91sam926x_timer_suspend NULL
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#endif
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struct sys_timer at91sam926x_timer = {
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.init = at91sam926x_timer_init,
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.offset = at91sam926x_gettimeoffset,
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.suspend = at91sam926x_timer_suspend,
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.resume = at91sam926x_timer_reset,
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.init = at91sam926x_pit_init,
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.suspend = at91sam926x_pit_suspend,
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.resume = at91sam926x_pit_reset,
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};
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