Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git branch HEAD
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commit
c1ef1f351d
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@ -383,6 +383,17 @@ static void __init process_switch(char c)
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/* Use PROM debug console. */
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register_console(&prom_debug_console);
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break;
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case 'P':
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/* Force UltraSPARC-III P-Cache on. */
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if (tlb_type != cheetah) {
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printk("BOOT: Ignoring P-Cache force option.\n");
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break;
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}
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cheetah_pcache_forced_on = 1;
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add_taint(TAINT_MACHINE_CHECK);
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cheetah_enable_pcache();
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break;
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default:
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printk("Unknown boot switch (-%c)\n", c);
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break;
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@ -123,6 +123,9 @@ void __init smp_callin(void)
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smp_setup_percpu_timer();
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if (cheetah_pcache_forced_on)
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cheetah_enable_pcache();
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local_irq_enable();
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calibrate_delay();
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@ -421,6 +421,25 @@ asmlinkage void cee_log(unsigned long ce_status,
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}
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}
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int cheetah_pcache_forced_on;
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void cheetah_enable_pcache(void)
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{
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unsigned long dcr;
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printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
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smp_processor_id());
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__asm__ __volatile__("ldxa [%%g0] %1, %0"
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: "=r" (dcr)
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: "i" (ASI_DCU_CONTROL_REG));
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dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
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__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
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}
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/* Cheetah error trap handling. */
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static unsigned long ecache_flush_physbase;
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static unsigned long ecache_flush_linesize;
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@ -151,6 +151,8 @@ static struct ata_port_info pdc_port_info[] = {
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static struct pci_device_id pdc_ata_pci_tbl[] = {
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{ PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_2037x },
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{ PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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@ -82,6 +82,7 @@ static struct pci_device_id sil_pci_tbl[] = {
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{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
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{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ } /* terminate list */
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};
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@ -48,6 +48,9 @@ enum ultra_tlb_layout {
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extern enum ultra_tlb_layout tlb_type;
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extern int cheetah_pcache_forced_on;
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extern void cheetah_enable_pcache(void);
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#define sparc64_highest_locked_tlbent() \
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(tlb_type == spitfire ? \
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SPITFIRE_HIGHEST_LOCKED_TLBENT : \
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