dw_dmac: add cyclic API to DW DMA driver
This patch adds a cyclic DMA interface to the DW DMA driver. This is very useful if you want to use the DMA controller in combination with a sound device which uses cyclic buffers. Using a DMA channel for cyclic DMA will disable the possibility to use it as a normal DMA engine until the user calls the cyclic free function on the DMA channel. Also a cyclic DMA list can not be prepared if the channel is already active. Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Hans-Christian Egtvedt
Dan Williams
parent
0f571515c3
commit
d9de451989
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@ -363,6 +363,82 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
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dwc_descriptor_complete(dwc, bad_desc);
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}
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/* --------------------- Cyclic DMA API extensions -------------------- */
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inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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return channel_readl(dwc, SAR);
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}
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EXPORT_SYMBOL(dw_dma_get_src_addr);
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inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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return channel_readl(dwc, DAR);
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}
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EXPORT_SYMBOL(dw_dma_get_dst_addr);
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/* called with dwc->lock held and all DMAC interrupts disabled */
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static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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u32 status_block, u32 status_err, u32 status_xfer)
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{
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if (status_block & dwc->mask) {
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void (*callback)(void *param);
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void *callback_param;
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dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
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channel_readl(dwc, LLP));
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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callback = dwc->cdesc->period_callback;
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callback_param = dwc->cdesc->period_callback_param;
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if (callback) {
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spin_unlock(&dwc->lock);
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callback(callback_param);
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spin_lock(&dwc->lock);
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}
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}
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/*
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* Error and transfer complete are highly unlikely, and will most
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* likely be due to a configuration error by the user.
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*/
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if (unlikely(status_err & dwc->mask) ||
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unlikely(status_xfer & dwc->mask)) {
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int i;
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dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
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"interrupt, stopping DMA transfer\n",
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status_xfer ? "xfer" : "error");
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dev_err(chan2dev(&dwc->chan),
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" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
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channel_readl(dwc, SAR),
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channel_readl(dwc, DAR),
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channel_readl(dwc, LLP),
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channel_readl(dwc, CTL_HI),
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channel_readl(dwc, CTL_LO));
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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/* make sure DMA does not restart by loading a new list */
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channel_writel(dwc, LLP, 0);
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channel_writel(dwc, CTL_LO, 0);
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channel_writel(dwc, CTL_HI, 0);
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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for (i = 0; i < dwc->cdesc->periods; i++)
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dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
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}
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}
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/* ------------------------------------------------------------------------- */
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static void dw_dma_tasklet(unsigned long data)
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{
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struct dw_dma *dw = (struct dw_dma *)data;
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@ -382,7 +458,10 @@ static void dw_dma_tasklet(unsigned long data)
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for (i = 0; i < dw->dma.chancnt; i++) {
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dwc = &dw->chan[i];
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spin_lock(&dwc->lock);
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if (status_err & (1 << i))
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
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dwc_handle_cyclic(dw, dwc, status_block, status_err,
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status_xfer);
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else if (status_err & (1 << i))
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dwc_handle_error(dw, dwc);
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else if ((status_block | status_xfer) & (1 << i))
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dwc_scan_descriptors(dw, dwc);
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@ -883,6 +962,257 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
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}
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/* --------------------- Cyclic DMA API extensions -------------------- */
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/**
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* dw_dma_cyclic_start - start the cyclic DMA transfer
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* @chan: the DMA channel to start
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*
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* Must be called with soft interrupts disabled. Returns zero on success or
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* -errno on failure.
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*/
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int dw_dma_cyclic_start(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
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dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
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return -ENODEV;
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}
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spin_lock(&dwc->lock);
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/* assert channel is idle */
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if (dma_readl(dw, CH_EN) & dwc->mask) {
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dev_err(chan2dev(&dwc->chan),
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"BUG: Attempted to start non-idle channel\n");
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dev_err(chan2dev(&dwc->chan),
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" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
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channel_readl(dwc, SAR),
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channel_readl(dwc, DAR),
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channel_readl(dwc, LLP),
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channel_readl(dwc, CTL_HI),
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channel_readl(dwc, CTL_LO));
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spin_unlock(&dwc->lock);
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return -EBUSY;
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}
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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/* setup DMAC channel registers */
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channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
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channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
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channel_writel(dwc, CTL_HI, 0);
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channel_set_bit(dw, CH_EN, dwc->mask);
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spin_unlock(&dwc->lock);
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return 0;
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}
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EXPORT_SYMBOL(dw_dma_cyclic_start);
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/**
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* dw_dma_cyclic_stop - stop the cyclic DMA transfer
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* @chan: the DMA channel to stop
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*
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* Must be called with soft interrupts disabled.
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*/
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void dw_dma_cyclic_stop(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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spin_lock(&dwc->lock);
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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spin_unlock(&dwc->lock);
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}
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EXPORT_SYMBOL(dw_dma_cyclic_stop);
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/**
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* dw_dma_cyclic_prep - prepare the cyclic DMA transfer
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* @chan: the DMA channel to prepare
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* @buf_addr: physical DMA address where the buffer starts
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* @buf_len: total number of bytes for the entire buffer
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* @period_len: number of bytes for each period
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* @direction: transfer direction, to or from device
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*
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* Must be called before trying to start the transfer. Returns a valid struct
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* dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
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*/
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_data_direction direction)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_cyclic_desc *cdesc;
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struct dw_cyclic_desc *retval = NULL;
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struct dw_desc *desc;
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struct dw_desc *last = NULL;
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struct dw_dma_slave *dws = chan->private;
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unsigned long was_cyclic;
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unsigned int reg_width;
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unsigned int periods;
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unsigned int i;
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spin_lock_bh(&dwc->lock);
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if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
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spin_unlock_bh(&dwc->lock);
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dev_dbg(chan2dev(&dwc->chan),
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"queue and/or active list are not empty\n");
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return ERR_PTR(-EBUSY);
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}
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was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
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spin_unlock_bh(&dwc->lock);
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if (was_cyclic) {
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dev_dbg(chan2dev(&dwc->chan),
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"channel already prepared for cyclic DMA\n");
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return ERR_PTR(-EBUSY);
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}
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retval = ERR_PTR(-EINVAL);
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reg_width = dws->reg_width;
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periods = buf_len / period_len;
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/* Check for too big/unaligned periods and unaligned DMA buffer. */
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if (period_len > (DWC_MAX_COUNT << reg_width))
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goto out_err;
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if (unlikely(period_len & ((1 << reg_width) - 1)))
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goto out_err;
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if (unlikely(buf_addr & ((1 << reg_width) - 1)))
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goto out_err;
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if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
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goto out_err;
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retval = ERR_PTR(-ENOMEM);
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if (periods > NR_DESCS_PER_CHANNEL)
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goto out_err;
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cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
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if (!cdesc)
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goto out_err;
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cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
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if (!cdesc->desc)
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goto out_err_alloc;
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for (i = 0; i < periods; i++) {
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desc = dwc_desc_get(dwc);
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if (!desc)
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goto out_err_desc_get;
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switch (direction) {
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case DMA_TO_DEVICE:
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desc->lli.dar = dws->tx_reg;
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desc->lli.sar = buf_addr + (period_len * i);
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desc->lli.ctllo = (DWC_DEFAULT_CTLLO
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| DWC_CTLL_DST_WIDTH(reg_width)
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| DWC_CTLL_SRC_WIDTH(reg_width)
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| DWC_CTLL_DST_FIX
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| DWC_CTLL_SRC_INC
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| DWC_CTLL_FC_M2P
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| DWC_CTLL_INT_EN);
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break;
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case DMA_FROM_DEVICE:
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desc->lli.dar = buf_addr + (period_len * i);
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desc->lli.sar = dws->rx_reg;
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desc->lli.ctllo = (DWC_DEFAULT_CTLLO
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| DWC_CTLL_SRC_WIDTH(reg_width)
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| DWC_CTLL_DST_WIDTH(reg_width)
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| DWC_CTLL_DST_INC
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| DWC_CTLL_SRC_FIX
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| DWC_CTLL_FC_P2M
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| DWC_CTLL_INT_EN);
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break;
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default:
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break;
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}
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desc->lli.ctlhi = (period_len >> reg_width);
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cdesc->desc[i] = desc;
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if (last) {
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last->lli.llp = desc->txd.phys;
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dma_sync_single_for_device(chan2parent(chan),
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last->txd.phys, sizeof(last->lli),
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DMA_TO_DEVICE);
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}
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last = desc;
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}
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/* lets make a cyclic list */
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last->lli.llp = cdesc->desc[0]->txd.phys;
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dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
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sizeof(last->lli), DMA_TO_DEVICE);
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dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
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"period %zu periods %d\n", buf_addr, buf_len,
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period_len, periods);
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cdesc->periods = periods;
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dwc->cdesc = cdesc;
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return cdesc;
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out_err_desc_get:
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while (i--)
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dwc_desc_put(dwc, cdesc->desc[i]);
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out_err_alloc:
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kfree(cdesc);
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out_err:
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clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
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return (struct dw_cyclic_desc *)retval;
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}
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EXPORT_SYMBOL(dw_dma_cyclic_prep);
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/**
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* dw_dma_cyclic_free - free a prepared cyclic DMA transfer
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* @chan: the DMA channel to free
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*/
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void dw_dma_cyclic_free(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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struct dw_cyclic_desc *cdesc = dwc->cdesc;
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int i;
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dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
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if (!cdesc)
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return;
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spin_lock_bh(&dwc->lock);
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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spin_unlock_bh(&dwc->lock);
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for (i = 0; i < cdesc->periods; i++)
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dwc_desc_put(dwc, cdesc->desc[i]);
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kfree(cdesc->desc);
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kfree(cdesc);
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clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
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}
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EXPORT_SYMBOL(dw_dma_cyclic_free);
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/*----------------------------------------------------------------------*/
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static void dw_dma_off(struct dw_dma *dw)
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@ -126,6 +126,10 @@ struct dw_dma_regs {
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#define DW_REGLEN 0x400
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enum dw_dmac_flags {
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DW_DMA_IS_CYCLIC = 0,
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};
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struct dw_dma_chan {
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struct dma_chan chan;
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void __iomem *ch_regs;
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@ -134,10 +138,12 @@ struct dw_dma_chan {
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spinlock_t lock;
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/* these other elements are all protected by lock */
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unsigned long flags;
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dma_cookie_t completed;
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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struct dw_cyclic_desc *cdesc;
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unsigned int descs_allocated;
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};
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@ -158,7 +164,6 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
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return container_of(chan, struct dw_dma_chan, chan);
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}
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struct dw_dma {
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struct dma_device dma;
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void __iomem *regs;
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@ -74,4 +74,23 @@ struct dw_dma_slave {
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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/* DMA API extensions */
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struct dw_cyclic_desc {
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struct dw_desc **desc;
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unsigned long periods;
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void (*period_callback)(void *param);
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void *period_callback_param;
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};
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_data_direction direction);
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void dw_dma_cyclic_free(struct dma_chan *chan);
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int dw_dma_cyclic_start(struct dma_chan *chan);
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void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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#endif /* DW_DMAC_H */
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