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sh: Fix SH-3 cache entry_mask and way_size calculation. 

The code for performing the calculation was only in the SH-4 probe
path, move it out to the common path so the other parts get this
right too.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2007-03-12 16:15:22 +09:00
parent fbd168461e
commit ffe1b4e9f4
2 changed files with 17 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/sh/kernel/cpu/init.c
View File

@ -3,7 +3,7 @@
*
* CPU init code
*
* Copyright (C) 2002 - 2006 Paul Mundt
* Copyright (C) 2002 - 2007 Paul Mundt
* Copyright (C) 2003 Richard Curnow
*
* This file is subject to the terms and conditions of the GNU General Public
@ -48,8 +48,19 @@ static void __init cache_init(void)
{
unsigned long ccr, flags;
if (current_cpu_data.type == CPU_SH_NONE)
panic("Unknown CPU");
/* First setup the rest of the I-cache info */
current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
current_cpu_data.icache.linesz;
current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
current_cpu_data.icache.linesz;
/* And the D-cache too */
current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
current_cpu_data.dcache.linesz;
current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
current_cpu_data.dcache.linesz;
jump_to_P2();
ccr = ctrl_inl(CCR);
@ -200,6 +211,9 @@ asmlinkage void __init sh_cpu_init(void)
/* First, probe the CPU */
detect_cpu_and_cache_system();
if (current_cpu_data.type == CPU_SH_NONE)
panic("Unknown CPU");
/* Init the cache */
cache_init();

13
arch/sh/kernel/cpu/sh4/probe.c
View File

@ -195,13 +195,6 @@ int __init detect_cpu_and_cache_system(void)
}
/* Setup the rest of the I-cache info */
current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
current_cpu_data.icache.linesz;
current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
current_cpu_data.icache.linesz;
/* And the rest of the D-cache */
if (current_cpu_data.dcache.ways > 1) {
size = sizes[(cvr >> 16) & 0xf];
@ -209,12 +202,6 @@ int __init detect_cpu_and_cache_system(void)
current_cpu_data.dcache.sets = (size >> 6);
}
current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
current_cpu_data.dcache.linesz;
current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
current_cpu_data.dcache.linesz;
/*
* Setup the L2 cache desc
*