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3 Commits

Author SHA1 Message Date
Stepan Moskovchenko 08bd683978 msm: iommu: Definitions for extended memory attributes 
Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
 2010-11-30 16:05:05 -08:00
Stepan Moskovchenko 23513c3b39 msm: iommu: Increase maximum MID size to 5 bits 
On msm8x60, the MID field on the AXI connection to the
IOMMU can be up to five bits wide. Thus, allow the IOMMU
context platform data to map up to 32 MIDs.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
 2010-11-30 13:53:08 -08:00
Stepan Moskovchenko 0720d1f052 msm: Add MSM IOMMU support 
Add support for the IOMMUs found on the upcoming Qualcomm
MSM8x60 chips. These IOMMUs allow virtualization of the
address space used by most of the multimedia cores on these
chips.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
 2010-10-08 15:12:50 -07:00