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Author SHA1 Message Date
David S. Miller ed6b0b4543 [SPARC64]: SUN4V memory exception trap handlers. 
Signed-off-by: David S. Miller <davem@davemloft.net>
 2006-03-20 01:12:07 -08:00
David S. Miller aa9143b971 [SPARC64]: Implement sun4v TSB miss handlers. 
When we register a TSB with the hypervisor, so that it or hardware can
handle TLB misses and do the TSB walk for us, the hypervisor traps
down to these trap when it incurs a TSB miss.

Processing is simple, we load the missing virtual address and context,
and do a full page table walk.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2006-03-20 01:12:05 -08:00
David S. Miller d257d5da39 [SPARC64]: Initial sun4v TLB miss handling infrastructure. 
Things are a little tricky because, unlike sun4u, we have
to:

1) do a hypervisor trap to do the TLB load.
2) do the TSB lookup calculations by hand

Signed-off-by: David S. Miller <davem@davemloft.net>
 2006-03-20 01:11:52 -08:00