204 lines
5.6 KiB
C
204 lines
5.6 KiB
C
/*
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* Copyright (C) 2005 Intel Corporation
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* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* - Added _PDC for SMP C-states on Intel CPUs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <acpi/processor.h>
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#include <asm/acpi.h>
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#include <asm/mwait.h>
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/*
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* Initialize bm_flags based on the CPU cache properties
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* On SMP it depends on cache configuration
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* - When cache is not shared among all CPUs, we flush cache
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* before entering C3.
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* - When cache is shared among all CPUs, we use bm_check
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* mechanism as in UP case
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*
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* This routine is called only after all the CPUs are online
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*/
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void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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unsigned int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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flags->bm_check = 0;
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if (num_online_cpus() == 1)
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flags->bm_check = 1;
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else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Today all MP CPUs that support C3 share cache.
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* And caches should not be flushed by software while
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* entering C3 type state.
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*/
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flags->bm_check = 1;
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}
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/*
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* On all recent Intel platforms, ARB_DISABLE is a nop.
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* So, set bm_control to zero to indicate that ARB_DISABLE
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* is not required while entering C3 type state on
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* P4, Core and beyond CPUs
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*/
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
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flags->bm_control = 0;
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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/* The code below handles cstate entry with monitor-mwait pair on Intel*/
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struct cstate_entry {
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struct {
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unsigned int eax;
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unsigned int ecx;
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} states[ACPI_PROCESSOR_MAX_POWER];
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};
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static struct cstate_entry __percpu *cpu_cstate_entry; /* per CPU ptr */
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static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
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#define NATIVE_CSTATE_BEYOND_HALT (2)
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static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
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{
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struct acpi_processor_cx *cx = _cx;
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long retval;
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unsigned int eax, ebx, ecx, edx;
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unsigned int edx_part;
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unsigned int cstate_type; /* C-state type and not ACPI C-state type */
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unsigned int num_cstate_subtype;
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cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
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/* Check whether this particular cx_type (in CST) is supported or not */
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cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
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MWAIT_CSTATE_MASK) + 1;
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edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
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num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
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retval = 0;
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if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
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retval = -1;
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goto out;
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}
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/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
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if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
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!(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
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retval = -1;
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goto out;
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}
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if (!mwait_supported[cstate_type]) {
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mwait_supported[cstate_type] = 1;
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printk(KERN_DEBUG
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"Monitor-Mwait will be used to enter C-%d "
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"state\n", cx->type);
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}
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snprintf(cx->desc,
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ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
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cx->address);
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out:
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return retval;
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}
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int acpi_processor_ffh_cstate_probe(unsigned int cpu,
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struct acpi_processor_cx *cx, struct acpi_power_register *reg)
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{
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struct cstate_entry *percpu_entry;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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long retval;
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if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
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return -1;
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if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
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return -1;
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percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
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percpu_entry->states[cx->index].eax = 0;
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percpu_entry->states[cx->index].ecx = 0;
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/* Make sure we are running on right CPU */
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retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
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if (retval == 0) {
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/* Use the hint in CST */
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percpu_entry->states[cx->index].eax = cx->address;
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percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
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}
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/*
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* For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
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* then we should skip checking BM_STS for this C-state.
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* ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
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*/
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if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
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cx->bm_sts_skip = 1;
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return retval;
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}
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EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
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/*
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* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
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* which can obviate IPI to trigger checking of need_resched.
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* We execute MONITOR against need_resched and enter optimized wait state
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* through MWAIT. Whenever someone changes need_resched, we would be woken
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* up from MWAIT (without an IPI).
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*
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* New with Core Duo processors, MWAIT can take some hints based on CPU
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* capability.
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*/
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void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
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{
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if (!need_resched()) {
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if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(ax, cx);
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}
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}
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void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
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{
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unsigned int cpu = smp_processor_id();
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struct cstate_entry *percpu_entry;
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percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
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mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
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percpu_entry->states[cx->index].ecx);
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}
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EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
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static int __init ffh_cstate_init(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (c->x86_vendor != X86_VENDOR_INTEL)
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return -1;
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cpu_cstate_entry = alloc_percpu(struct cstate_entry);
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return 0;
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}
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static void __exit ffh_cstate_exit(void)
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{
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free_percpu(cpu_cstate_entry);
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cpu_cstate_entry = NULL;
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}
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arch_initcall(ffh_cstate_init);
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__exitcall(ffh_cstate_exit);
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