620 lines
14 KiB
C
620 lines
14 KiB
C
/*
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* drivers/mtd/nand/au1550nd.c
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*
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* Copyright (C) 2004 Embedded Edge, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#ifdef CONFIG_MIPS_PB1550
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#include <asm/mach-pb1x00/pb1550.h>
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#elif defined(CONFIG_MIPS_DB1550)
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#include <asm/mach-db1x00/db1x00.h>
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#endif
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#include <asm/mach-db1x00/bcsr.h>
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/*
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* MTD structure for NAND controller
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*/
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static struct mtd_info *au1550_mtd = NULL;
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static void __iomem *p_nand;
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static int nand_width = 1; /* default x8 */
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static void (*au1550_write_byte)(struct mtd_info *, u_char);
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/*
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* Define partitions for flash device
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*/
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static const struct mtd_partition partition_info[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL}
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};
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/**
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* au_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*
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* read function for 8bit buswidth
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*/
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static u_char au_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = readb(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_byte - write one byte to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 8it buswidth
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*/
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static void au_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writeb(byte, this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_byte16 - read one byte endianness aware from the chip
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* @mtd: MTD device structure
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*
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* read function for 16bit buswidth with endianness conversion
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*/
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static u_char au_read_byte16(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
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au_sync();
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return ret;
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}
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/**
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* au_write_byte16 - write one byte endianness aware to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 16bit buswidth with endianness conversion
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*/
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static void au_write_byte16(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_word - read one word from the chip
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* @mtd: MTD device structure
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*
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* read function for 16bit buswidth without endianness conversion
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*/
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static u16 au_read_word(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u16 ret = readw(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 8bit buswidth
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*/
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static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++) {
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writeb(buf[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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* au_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 8bit buswidth
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*/
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static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++) {
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buf[i] = readb(this->IO_ADDR_R);
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au_sync();
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}
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}
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/**
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* au_verify_buf - Verify chip data against buffer
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 8bit buswidth
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*/
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static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++) {
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if (buf[i] != readb(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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/**
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* au_write_buf16 - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 16bit buswidth
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*/
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static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++) {
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writew(p[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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* au_read_buf16 - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 16bit buswidth
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*/
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static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++) {
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p[i] = readw(this->IO_ADDR_R);
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au_sync();
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}
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}
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/**
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* au_verify_buf16 - Verify chip data against buffer
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*
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* verify function for 16bit buswidth
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*/
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static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++) {
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if (p[i] != readw(this->IO_ADDR_R))
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return -EFAULT;
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au_sync();
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}
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return 0;
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}
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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register struct nand_chip *this = mtd->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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break;
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
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break;
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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/* FIXME: Nobody knows why this is necessary,
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* but it works only that way */
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udelay(1);
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break;
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case NAND_CTL_SETNCE:
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/* assert (force assert) chip enable */
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au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
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break;
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case NAND_CTL_CLRNCE:
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/* deassert chip enable */
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au_writel(0, MEM_STNDCTL);
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break;
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}
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this->IO_ADDR_R = this->IO_ADDR_W;
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/* Drain the writebuffer */
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au_sync();
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}
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int au1550_device_ready(struct mtd_info *mtd)
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{
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int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
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au_sync();
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return ret;
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}
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/**
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* au1550_select_chip - control -CE line
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* Forbid driving -CE manually permitting the NAND controller to do this.
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* Keeping -CE asserted during the whole sector reads interferes with the
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* NOR flash and PCMCIA drivers as it causes contention on the static bus.
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* We only have to hold -CE low for the NAND read commands since the flash
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* chip needs it to be asserted during chip not ready time but the NAND
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* controller keeps it released.
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*
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* @mtd: MTD device structure
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* @chip: chipnumber to select, -1 for deselect
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*/
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static void au1550_select_chip(struct mtd_info *mtd, int chip)
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{
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}
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/**
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* au1550_command - Send command to NAND device
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* @mtd: MTD device structure
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* @command: the command to be sent
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* @column: the column address for this command, -1 if none
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* @page_addr: the page address for this command, -1 if none
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*/
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static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
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{
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register struct nand_chip *this = mtd->priv;
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int ce_override = 0, i;
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ulong flags;
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/* Begin command latch cycle */
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au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->writesize) {
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/* OOB area */
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column -= mtd->writesize;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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au1550_write_byte(mtd, readcmd);
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}
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au1550_write_byte(mtd, command);
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/* Set ALE and clear CLE to start address cycle */
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au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
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if (column != -1 || page_addr != -1) {
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au1550_hwcontrol(mtd, NAND_CTL_SETALE);
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (this->options & NAND_BUSWIDTH_16)
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column >>= 1;
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au1550_write_byte(mtd, column);
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}
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if (page_addr != -1) {
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au1550_write_byte(mtd, (u8)(page_addr & 0xff));
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if (command == NAND_CMD_READ0 ||
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command == NAND_CMD_READ1 ||
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command == NAND_CMD_READOOB) {
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/*
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* NAND controller will release -CE after
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* the last address byte is written, so we'll
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* have to forcibly assert it. No interrupts
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* are allowed while we do this as we don't
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* want the NOR flash or PCMCIA drivers to
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* steal our precious bytes of data...
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*/
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ce_override = 1;
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local_irq_save(flags);
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au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
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}
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au1550_write_byte(mtd, (u8)(page_addr >> 8));
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/* One more address cycle for devices > 32MiB */
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if (this->chipsize > (32 << 20))
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au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
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}
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/*
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* Program and erase have their own busy handlers.
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* Status and sequential in need no delay.
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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break;
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case NAND_CMD_READ0:
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case NAND_CMD_READ1:
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case NAND_CMD_READOOB:
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/* Check if we're really driving -CE low (just in case) */
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if (unlikely(!ce_override))
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break;
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/* Apply a short delay always to ensure that we do wait tWB. */
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ndelay(100);
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/* Wait for a chip to become ready... */
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for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
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udelay(1);
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/* Release -CE and re-enable interrupts. */
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au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
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local_irq_restore(flags);
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return;
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}
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/* Apply this short delay always to ensure that we do wait tWB. */
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ndelay(100);
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while(!this->dev_ready(mtd));
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}
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/*
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* Main initialization routine
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*/
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static int __init au1xxx_nand_init(void)
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{
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struct nand_chip *this;
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u16 boot_swapboot = 0; /* default value */
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int retval;
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u32 mem_staddr;
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u32 nand_phys;
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/* Allocate memory for MTD device structure and private data */
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au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
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if (!au1550_mtd) {
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printk("Unable to allocate NAND MTD dev structure.\n");
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return -ENOMEM;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&au1550_mtd[1]);
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/* Link the private data with the MTD structure */
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au1550_mtd->priv = this;
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au1550_mtd->owner = THIS_MODULE;
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/* MEM_STNDCTL: disable ints, disable nand boot */
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au_writel(0, MEM_STNDCTL);
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#ifdef CONFIG_MIPS_PB1550
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/* set gpio206 high */
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gpio_direction_input(206);
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boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
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switch (boot_swapboot) {
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case 0:
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case 2:
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case 8:
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case 0xC:
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case 0xD:
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/* x16 NAND Flash */
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nand_width = 0;
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break;
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case 1:
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case 9:
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case 3:
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case 0xE:
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case 0xF:
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/* x8 NAND Flash */
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nand_width = 1;
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break;
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default:
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printk("Pb1550 NAND: bad boot:swap\n");
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retval = -EINVAL;
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goto outmem;
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}
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#endif
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/* Configure chip-select; normally done by boot code, e.g. YAMON */
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#ifdef NAND_STCFG
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if (NAND_CS == 0) {
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au_writel(NAND_STCFG, MEM_STCFG0);
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au_writel(NAND_STTIME, MEM_STTIME0);
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au_writel(NAND_STADDR, MEM_STADDR0);
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}
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if (NAND_CS == 1) {
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au_writel(NAND_STCFG, MEM_STCFG1);
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au_writel(NAND_STTIME, MEM_STTIME1);
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au_writel(NAND_STADDR, MEM_STADDR1);
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}
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if (NAND_CS == 2) {
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au_writel(NAND_STCFG, MEM_STCFG2);
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au_writel(NAND_STTIME, MEM_STTIME2);
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au_writel(NAND_STADDR, MEM_STADDR2);
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}
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if (NAND_CS == 3) {
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au_writel(NAND_STCFG, MEM_STCFG3);
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au_writel(NAND_STTIME, MEM_STTIME3);
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au_writel(NAND_STADDR, MEM_STADDR3);
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}
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#endif
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/* Locate NAND chip-select in order to determine NAND phys address */
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mem_staddr = 0x00000000;
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if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
|
|
mem_staddr = au_readl(MEM_STADDR0);
|
|
else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
|
|
mem_staddr = au_readl(MEM_STADDR1);
|
|
else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
|
|
mem_staddr = au_readl(MEM_STADDR2);
|
|
else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
|
|
mem_staddr = au_readl(MEM_STADDR3);
|
|
|
|
if (mem_staddr == 0x00000000) {
|
|
printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
|
|
kfree(au1550_mtd);
|
|
return 1;
|
|
}
|
|
nand_phys = (mem_staddr << 4) & 0xFFFC0000;
|
|
|
|
p_nand = ioremap(nand_phys, 0x1000);
|
|
|
|
/* make controller and MTD agree */
|
|
if (NAND_CS == 0)
|
|
nand_width = au_readl(MEM_STCFG0) & (1 << 22);
|
|
if (NAND_CS == 1)
|
|
nand_width = au_readl(MEM_STCFG1) & (1 << 22);
|
|
if (NAND_CS == 2)
|
|
nand_width = au_readl(MEM_STCFG2) & (1 << 22);
|
|
if (NAND_CS == 3)
|
|
nand_width = au_readl(MEM_STCFG3) & (1 << 22);
|
|
|
|
/* Set address of hardware control function */
|
|
this->dev_ready = au1550_device_ready;
|
|
this->select_chip = au1550_select_chip;
|
|
this->cmdfunc = au1550_command;
|
|
|
|
/* 30 us command delay time */
|
|
this->chip_delay = 30;
|
|
this->ecc.mode = NAND_ECC_SOFT;
|
|
|
|
this->options = NAND_NO_AUTOINCR;
|
|
|
|
if (!nand_width)
|
|
this->options |= NAND_BUSWIDTH_16;
|
|
|
|
this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
|
|
au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
|
|
this->read_word = au_read_word;
|
|
this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
|
|
this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
|
|
this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
|
|
|
|
/* Scan to find existence of the device */
|
|
if (nand_scan(au1550_mtd, 1)) {
|
|
retval = -ENXIO;
|
|
goto outio;
|
|
}
|
|
|
|
/* Register the partitions */
|
|
mtd_device_register(au1550_mtd, partition_info,
|
|
ARRAY_SIZE(partition_info));
|
|
|
|
return 0;
|
|
|
|
outio:
|
|
iounmap(p_nand);
|
|
|
|
outmem:
|
|
kfree(au1550_mtd);
|
|
return retval;
|
|
}
|
|
|
|
module_init(au1xxx_nand_init);
|
|
|
|
/*
|
|
* Clean up routine
|
|
*/
|
|
static void __exit au1550_cleanup(void)
|
|
{
|
|
/* Release resources, unregister device */
|
|
nand_release(au1550_mtd);
|
|
|
|
/* Free the MTD device structure */
|
|
kfree(au1550_mtd);
|
|
|
|
/* Unmap */
|
|
iounmap(p_nand);
|
|
}
|
|
|
|
module_exit(au1550_cleanup);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Embedded Edge, LLC");
|
|
MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
|