453 lines
13 KiB
C
453 lines
13 KiB
C
/*
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* esb2rom.c
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*
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* Normal mappings of flash chips in physical memory
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* through the Intel ESB2 Southbridge.
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*
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* This was derived from ichxrom.c in May 2006 by
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* Lew Glendenning <lglendenning@lnxi.com>
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*
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* Eric Biederman, of course, was a major help in this effort.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/cfi.h>
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#include <linux/mtd/flashchip.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/list.h>
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#define MOD_NAME KBUILD_BASENAME
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#define ADDRESS_NAME_LEN 18
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#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
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#define BIOS_CNTL 0xDC
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#define BIOS_LOCK_ENABLE 0x02
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#define BIOS_WRITE_ENABLE 0x01
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/* This became a 16-bit register, and EN2 has disappeared */
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#define FWH_DEC_EN1 0xD8
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#define FWH_F8_EN 0x8000
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#define FWH_F0_EN 0x4000
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#define FWH_E8_EN 0x2000
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#define FWH_E0_EN 0x1000
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#define FWH_D8_EN 0x0800
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#define FWH_D0_EN 0x0400
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#define FWH_C8_EN 0x0200
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#define FWH_C0_EN 0x0100
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#define FWH_LEGACY_F_EN 0x0080
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#define FWH_LEGACY_E_EN 0x0040
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/* reserved 0x0020 and 0x0010 */
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#define FWH_70_EN 0x0008
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#define FWH_60_EN 0x0004
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#define FWH_50_EN 0x0002
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#define FWH_40_EN 0x0001
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/* these are 32-bit values */
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#define FWH_SEL1 0xD0
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#define FWH_SEL2 0xD4
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#define FWH_8MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
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FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN)
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#define FWH_7MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
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FWH_70_EN | FWH_60_EN | FWH_50_EN)
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#define FWH_6MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
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FWH_70_EN | FWH_60_EN)
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#define FWH_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
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FWH_70_EN)
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#define FWH_4MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN)
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#define FWH_3_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN | FWH_C8_EN)
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#define FWH_3MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN | FWH_D0_EN)
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#define FWH_2_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
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FWH_D8_EN)
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#define FWH_2MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN)
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#define FWH_1_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN)
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#define FWH_1MiB (FWH_F8_EN | FWH_F0_EN)
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#define FWH_0_5MiB (FWH_F8_EN)
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struct esb2rom_window {
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void __iomem* virt;
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unsigned long phys;
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unsigned long size;
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struct list_head maps;
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struct resource rsrc;
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struct pci_dev *pdev;
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};
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struct esb2rom_map_info {
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struct list_head list;
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struct map_info map;
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struct mtd_info *mtd;
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struct resource rsrc;
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char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
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};
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static struct esb2rom_window esb2rom_window = {
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.maps = LIST_HEAD_INIT(esb2rom_window.maps),
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};
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static void esb2rom_cleanup(struct esb2rom_window *window)
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{
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struct esb2rom_map_info *map, *scratch;
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u8 byte;
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/* Disable writes through the rom window */
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pci_read_config_byte(window->pdev, BIOS_CNTL, &byte);
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pci_write_config_byte(window->pdev, BIOS_CNTL,
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byte & ~BIOS_WRITE_ENABLE);
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/* Free all of the mtd devices */
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list_for_each_entry_safe(map, scratch, &window->maps, list) {
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if (map->rsrc.parent)
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release_resource(&map->rsrc);
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del_mtd_device(map->mtd);
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map_destroy(map->mtd);
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list_del(&map->list);
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kfree(map);
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}
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if (window->rsrc.parent)
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release_resource(&window->rsrc);
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if (window->virt) {
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iounmap(window->virt);
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window->virt = NULL;
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window->phys = 0;
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window->size = 0;
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}
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pci_dev_put(window->pdev);
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}
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static int __devinit esb2rom_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
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struct esb2rom_window *window = &esb2rom_window;
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struct esb2rom_map_info *map = NULL;
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unsigned long map_top;
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u8 byte;
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u16 word;
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/* For now I just handle the ecb2 and I assume there
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* are not a lot of resources up at the top of the address
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* space. It is possible to handle other devices in the
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* top 16MiB but it is very painful. Also since
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* you can only really attach a FWH to an ICHX there
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* a number of simplifications you can make.
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*
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* Also you can page firmware hubs if an 8MiB window isn't enough
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* but don't currently handle that case either.
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*/
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window->pdev = pci_dev_get(pdev);
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/* RLG: experiment 2. Force the window registers to the widest values */
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/*
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pci_read_config_word(pdev, FWH_DEC_EN1, &word);
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printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word);
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pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff);
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pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
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printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte);
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pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
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printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte);
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pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f);
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pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
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printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte);
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*/
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/* Find a region continuous to the end of the ROM window */
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window->phys = 0;
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pci_read_config_word(pdev, FWH_DEC_EN1, &word);
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printk(KERN_DEBUG "pci_read_config_word : %x\n", word);
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if ((word & FWH_8MiB) == FWH_8MiB)
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window->phys = 0xff400000;
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else if ((word & FWH_7MiB) == FWH_7MiB)
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window->phys = 0xff500000;
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else if ((word & FWH_6MiB) == FWH_6MiB)
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window->phys = 0xff600000;
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else if ((word & FWH_5MiB) == FWH_5MiB)
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window->phys = 0xFF700000;
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else if ((word & FWH_4MiB) == FWH_4MiB)
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window->phys = 0xffc00000;
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else if ((word & FWH_3_5MiB) == FWH_3_5MiB)
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window->phys = 0xffc80000;
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else if ((word & FWH_3MiB) == FWH_3MiB)
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window->phys = 0xffd00000;
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else if ((word & FWH_2_5MiB) == FWH_2_5MiB)
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window->phys = 0xffd80000;
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else if ((word & FWH_2MiB) == FWH_2MiB)
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window->phys = 0xffe00000;
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else if ((word & FWH_1_5MiB) == FWH_1_5MiB)
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window->phys = 0xffe80000;
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else if ((word & FWH_1MiB) == FWH_1MiB)
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window->phys = 0xfff00000;
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else if ((word & FWH_0_5MiB) == FWH_0_5MiB)
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window->phys = 0xfff80000;
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if (window->phys == 0) {
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printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
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goto out;
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}
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/* reserved 0x0020 and 0x0010 */
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window->phys -= 0x400000UL;
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window->size = (0xffffffffUL - window->phys) + 1UL;
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/* Enable writes through the rom window */
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pci_read_config_byte(pdev, BIOS_CNTL, &byte);
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if (!(byte & BIOS_WRITE_ENABLE) && (byte & (BIOS_LOCK_ENABLE))) {
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/* The BIOS will generate an error if I enable
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* this device, so don't even try.
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*/
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printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
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goto out;
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}
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pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE);
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/*
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* Try to reserve the window mem region. If this fails then
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* it is likely due to the window being "reseved" by the BIOS.
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*/
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window->rsrc.name = MOD_NAME;
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window->rsrc.start = window->phys;
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window->rsrc.end = window->phys + window->size - 1;
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window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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if (request_resource(&iomem_resource, &window->rsrc)) {
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window->rsrc.parent = NULL;
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printk(KERN_DEBUG MOD_NAME ": "
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"%s(): Unable to register resource %pR - kernel bug?\n",
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__func__, &window->rsrc);
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}
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/* Map the firmware hub into my address space. */
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window->virt = ioremap_nocache(window->phys, window->size);
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if (!window->virt) {
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printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
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window->phys, window->size);
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goto out;
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}
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/* Get the first address to look for an rom chip at */
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map_top = window->phys;
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if ((window->phys & 0x3fffff) != 0) {
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/* if not aligned on 4MiB, look 4MiB lower in address space */
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map_top = window->phys + 0x400000;
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}
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#if 1
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/* The probe sequence run over the firmware hub lock
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* registers sets them to 0x7 (no access).
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* (Insane hardware design, but most copied Intel's.)
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* ==> Probe at most the last 4M of the address space.
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*/
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if (map_top < 0xffc00000)
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map_top = 0xffc00000;
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#endif
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/* Loop through and look for rom chips */
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while ((map_top - 1) < 0xffffffffUL) {
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struct cfi_private *cfi;
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unsigned long offset;
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int i;
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if (!map)
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map = kmalloc(sizeof(*map), GFP_KERNEL);
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if (!map) {
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printk(KERN_ERR MOD_NAME ": kmalloc failed");
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goto out;
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}
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memset(map, 0, sizeof(*map));
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INIT_LIST_HEAD(&map->list);
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map->map.name = map->map_name;
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map->map.phys = map_top;
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offset = map_top - window->phys;
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map->map.virt = (void __iomem *)
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(((unsigned long)(window->virt)) + offset);
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map->map.size = 0xffffffffUL - map_top + 1UL;
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/* Set the name of the map to the address I am trying */
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sprintf(map->map_name, "%s @%08Lx",
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MOD_NAME, (unsigned long long)map->map.phys);
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/* Firmware hubs only use vpp when being programmed
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* in a factory setting. So in-place programming
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* needs to use a different method.
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*/
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for(map->map.bankwidth = 32; map->map.bankwidth;
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map->map.bankwidth >>= 1) {
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char **probe_type;
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/* Skip bankwidths that are not supported */
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if (!map_bankwidth_supported(map->map.bankwidth))
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continue;
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/* Setup the map methods */
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simple_map_init(&map->map);
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/* Try all of the probe methods */
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probe_type = rom_probe_types;
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for(; *probe_type; probe_type++) {
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map->mtd = do_map_probe(*probe_type, &map->map);
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if (map->mtd)
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goto found;
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}
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}
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map_top += ROM_PROBE_STEP_SIZE;
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continue;
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found:
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/* Trim the size if we are larger than the map */
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if (map->mtd->size > map->map.size) {
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printk(KERN_WARNING MOD_NAME
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" rom(%llu) larger than window(%lu). fixing...\n",
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(unsigned long long)map->mtd->size, map->map.size);
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map->mtd->size = map->map.size;
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}
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if (window->rsrc.parent) {
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/*
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* Registering the MTD device in iomem may not be possible
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* if there is a BIOS "reserved" and BUSY range. If this
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* fails then continue anyway.
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*/
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map->rsrc.name = map->map_name;
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map->rsrc.start = map->map.phys;
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map->rsrc.end = map->map.phys + map->mtd->size - 1;
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map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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if (request_resource(&window->rsrc, &map->rsrc)) {
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printk(KERN_ERR MOD_NAME
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": cannot reserve MTD resource\n");
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map->rsrc.parent = NULL;
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}
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}
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/* Make the whole region visible in the map */
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map->map.virt = window->virt;
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map->map.phys = window->phys;
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cfi = map->map.fldrv_priv;
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for(i = 0; i < cfi->numchips; i++)
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cfi->chips[i].start += offset;
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/* Now that the mtd devices is complete claim and export it */
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map->mtd->owner = THIS_MODULE;
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if (add_mtd_device(map->mtd)) {
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map_destroy(map->mtd);
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map->mtd = NULL;
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goto out;
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}
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/* Calculate the new value of map_top */
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map_top += map->mtd->size;
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/* File away the map structure */
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list_add(&map->list, &window->maps);
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map = NULL;
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}
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out:
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/* Free any left over map structures */
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kfree(map);
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/* See if I have any map structures */
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if (list_empty(&window->maps)) {
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esb2rom_cleanup(window);
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return -ENODEV;
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}
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return 0;
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}
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static void __devexit esb2rom_remove_one (struct pci_dev *pdev)
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{
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struct esb2rom_window *window = &esb2rom_window;
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esb2rom_cleanup(window);
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}
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static struct pci_device_id esb2rom_pci_tbl[] __devinitdata = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ 0, },
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};
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#if 0
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MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl);
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static struct pci_driver esb2rom_driver = {
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.name = MOD_NAME,
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.id_table = esb2rom_pci_tbl,
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.probe = esb2rom_init_one,
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.remove = esb2rom_remove_one,
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};
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#endif
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static int __init init_esb2rom(void)
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{
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struct pci_dev *pdev;
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struct pci_device_id *id;
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int retVal;
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pdev = NULL;
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for (id = esb2rom_pci_tbl; id->vendor; id++) {
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printk(KERN_DEBUG "device id = %x\n", id->device);
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pdev = pci_get_device(id->vendor, id->device, NULL);
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if (pdev) {
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printk(KERN_DEBUG "matched device = %x\n", id->device);
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break;
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}
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}
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if (pdev) {
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printk(KERN_DEBUG "matched device id %x\n", id->device);
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retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]);
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pci_dev_put(pdev);
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printk(KERN_DEBUG "retVal = %d\n", retVal);
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return retVal;
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}
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return -ENXIO;
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#if 0
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return pci_register_driver(&esb2rom_driver);
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#endif
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}
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static void __exit cleanup_esb2rom(void)
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{
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esb2rom_remove_one(esb2rom_window.pdev);
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}
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module_init(init_esb2rom);
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module_exit(cleanup_esb2rom);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>");
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MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge");
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