104 lines
2.6 KiB
C
104 lines
2.6 KiB
C
/**
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* op_model_v7.h
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* ARM v7 (Cortex A8) Event Monitor Driver
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*
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* Copyright 2008 Jean Pihet <jpihet@mvista.com>
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* Copyright 2004 ARM SMP Development Team
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* Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
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* Copyright 2000-2004 MontaVista Software Inc
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* Copyright 2004 Dave Jiang <dave.jiang@intel.com>
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* Copyright 2004 Intel Corporation
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* Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
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* Copyright 2004 Oprofile Authors
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*
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* Read the file COPYING
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OP_MODEL_V7_H
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#define OP_MODEL_V7_H
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/*
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* Per-CPU PMNC: config reg
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*/
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#define PMNC_E (1 << 0) /* Enable all counters */
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#define PMNC_P (1 << 1) /* Reset all counters */
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#define PMNC_C (1 << 2) /* Cycle counter reset */
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#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define PMNC_X (1 << 4) /* Export to ETM */
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#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define PMNC_MASK 0x3f /* Mask for writable bits */
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/*
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* Available counters
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*/
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#define CCNT 0
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#define CNT0 1
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#define CNT1 2
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#define CNT2 3
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#define CNT3 4
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#define CNTMAX 5
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#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter))
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/*
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* CNTENS: counters enable reg
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*/
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#define CNTENS_P0 (1 << 0)
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#define CNTENS_P1 (1 << 1)
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#define CNTENS_P2 (1 << 2)
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#define CNTENS_P3 (1 << 3)
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#define CNTENS_C (1 << 31)
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#define CNTENS_MASK 0x8000000f /* Mask for writable bits */
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/*
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* CNTENC: counters disable reg
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*/
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#define CNTENC_P0 (1 << 0)
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#define CNTENC_P1 (1 << 1)
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#define CNTENC_P2 (1 << 2)
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#define CNTENC_P3 (1 << 3)
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#define CNTENC_C (1 << 31)
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#define CNTENC_MASK 0x8000000f /* Mask for writable bits */
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/*
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* INTENS: counters overflow interrupt enable reg
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*/
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#define INTENS_P0 (1 << 0)
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#define INTENS_P1 (1 << 1)
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#define INTENS_P2 (1 << 2)
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#define INTENS_P3 (1 << 3)
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#define INTENS_C (1 << 31)
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#define INTENS_MASK 0x8000000f /* Mask for writable bits */
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/*
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* EVTSEL: Event selection reg
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*/
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#define EVTSEL_MASK 0x7f /* Mask for writable bits */
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/*
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* SELECT: Counter selection reg
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*/
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#define SELECT_MASK 0x1f /* Mask for writable bits */
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/*
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* FLAG: counters overflow flag status reg
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*/
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#define FLAG_P0 (1 << 0)
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#define FLAG_P1 (1 << 1)
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#define FLAG_P2 (1 << 2)
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#define FLAG_P3 (1 << 3)
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#define FLAG_C (1 << 31)
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#define FLAG_MASK 0x8000000f /* Mask for writable bits */
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int armv7_setup_pmu(void);
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int armv7_start_pmu(void);
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int armv7_stop_pmu(void);
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int armv7_request_interrupts(int *, int);
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void armv7_release_interrupts(int *, int);
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#endif
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