571 lines
15 KiB
C
571 lines
15 KiB
C
/*
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* davinci_nand.c - NAND Flash Driver for DaVinci family chips
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Port to 2.6.23 Copyright © 2008 by:
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <mach/nand.h>
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#include <asm/mach-types.h>
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/*
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* This is a device driver for the NAND flash controller found on the
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* various DaVinci family chips. It handles up to four SoC chipselects,
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* and some flavors of secondary chipselect (e.g. based on A12) as used
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* with multichip packages.
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*
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* The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC
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* available on chips like the DM355 and OMAP-L137 and needed with the
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* more error-prone MLC NAND chips.
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*
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* This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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* outputs in a "wire-AND" configuration, with no per-chip signals.
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*/
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struct davinci_nand_info {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct device *dev;
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struct clk *clk;
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bool partitioned;
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void __iomem *base;
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void __iomem *vaddr;
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uint32_t ioaddr;
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uint32_t current_cs;
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uint32_t mask_chipsel;
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uint32_t mask_ale;
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uint32_t mask_cle;
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uint32_t core_chipsel;
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};
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static DEFINE_SPINLOCK(davinci_nand_lock);
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#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
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static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
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int offset)
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{
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return __raw_readl(info->base + offset);
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}
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static inline void davinci_nand_writel(struct davinci_nand_info *info,
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int offset, unsigned long value)
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{
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__raw_writel(value, info->base + offset);
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}
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/*----------------------------------------------------------------------*/
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/*
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* Access to hardware control lines: ALE, CLE, secondary chipselect.
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*/
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->current_cs;
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struct nand_chip *nand = mtd->priv;
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/* Did the control lines change? */
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if (ctrl & NAND_CTRL_CHANGE) {
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if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
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addr |= info->mask_cle;
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else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
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addr |= info->mask_ale;
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nand->IO_ADDR_W = (void __iomem __force *)addr;
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}
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if (cmd != NAND_CMD_NONE)
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iowrite8(cmd, nand->IO_ADDR_W);
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}
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static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->ioaddr;
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/* maybe kick in a second chipselect */
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if (chip > 0)
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addr |= info->mask_chipsel;
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info->current_cs = addr;
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info->chip.IO_ADDR_W = (void __iomem __force *)addr;
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info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 1-bit hardware ECC ... context maintained for each core chipselect
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*/
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static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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return davinci_nand_readl(info, NANDF1ECC_OFFSET
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+ 4 * info->core_chipsel);
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}
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static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info;
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uint32_t nandcfr;
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unsigned long flags;
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info = to_davinci_nand(mtd);
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/* Reset ECC hardware */
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nand_davinci_readecc_1bit(mtd);
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spin_lock_irqsave(&davinci_nand_lock, flags);
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/* Restart ECC hardware */
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nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
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nandcfr |= BIT(8 + info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
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spin_unlock_irqrestore(&davinci_nand_lock, flags);
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}
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/*
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* Read hardware ECC value and pack into three bytes
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*/
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static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
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unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
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/* invert so that erased block ecc is correct */
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ecc24 = ~ecc24;
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ecc_code[0] = (u_char)(ecc24);
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ecc_code[1] = (u_char)(ecc24 >> 8);
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ecc_code[2] = (u_char)(ecc24 >> 16);
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return 0;
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}
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static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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uint32_t diff = eccCalc ^ eccNand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < chip->ecc.size) {
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dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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* nothing to fix */
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return 1;
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} else {
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/* Uncorrectable error */
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return -1;
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}
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}
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return 0;
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}
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/*----------------------------------------------------------------------*/
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/*
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* NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
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* how these chips are normally wired. This translates to both 8 and 16
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* bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
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*
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* For now we assume that configuration, or any other one which ignores
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* the two LSBs for NAND access ... so we can issue 32-bit reads/writes
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* and have that transparently morphed into multiple NAND operations.
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*/
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static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
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ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
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else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
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ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
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else
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ioread8_rep(chip->IO_ADDR_R, buf, len);
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}
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static void nand_davinci_write_buf(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
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iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
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else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
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iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
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else
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iowrite8_rep(chip->IO_ADDR_R, buf, len);
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}
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/*
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* Check hardware register for wait status. Returns 1 if device is ready,
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* 0 if it is still busy.
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*/
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static int nand_davinci_dev_ready(struct mtd_info *mtd)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
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}
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static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
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{
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uint32_t regval, a1cr;
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/*
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* NAND FLASH timings @ PLL1 == 459 MHz
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* - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz
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* - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
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*/
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regval = 0
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| (0 << 31) /* selectStrobe */
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| (0 << 30) /* extWait (never with NAND) */
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| (1 << 26) /* writeSetup 10 ns */
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| (3 << 20) /* writeStrobe 40 ns */
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| (1 << 17) /* writeHold 10 ns */
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| (0 << 13) /* readSetup 10 ns */
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| (3 << 7) /* readStrobe 60 ns */
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| (0 << 4) /* readHold 10 ns */
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| (3 << 2) /* turnAround ?? ns */
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| (0 << 0) /* asyncSize 8-bit bus */
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;
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a1cr = davinci_nand_readl(info, A1CR_OFFSET);
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if (a1cr != regval) {
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dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
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"reg to 0x%08x, was 0x%08x, should be done by " \
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"bootloader.\n", regval, a1cr);
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davinci_nand_writel(info, A1CR_OFFSET, regval);
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}
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}
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/*----------------------------------------------------------------------*/
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static int __init nand_davinci_probe(struct platform_device *pdev)
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{
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struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
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struct davinci_nand_info *info;
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struct resource *res1;
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struct resource *res2;
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void __iomem *vaddr;
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void __iomem *base;
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int ret;
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uint32_t val;
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nand_ecc_modes_t ecc_mode;
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/* which external chipselect will we be managing? */
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if (pdev->id < 0 || pdev->id > 3)
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return -ENODEV;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info) {
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dev_err(&pdev->dev, "unable to allocate memory\n");
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ret = -ENOMEM;
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goto err_nomem;
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}
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platform_set_drvdata(pdev, info);
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res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res1 || !res2) {
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dev_err(&pdev->dev, "resource missing\n");
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ret = -EINVAL;
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goto err_nomem;
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}
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vaddr = ioremap(res1->start, res1->end - res1->start);
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base = ioremap(res2->start, res2->end - res2->start);
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if (!vaddr || !base) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -EINVAL;
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goto err_ioremap;
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}
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info->dev = &pdev->dev;
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info->base = base;
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info->vaddr = vaddr;
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info->mtd.priv = &info->chip;
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info->mtd.name = dev_name(&pdev->dev);
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info->mtd.owner = THIS_MODULE;
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info->mtd.dev.parent = &pdev->dev;
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info->chip.IO_ADDR_R = vaddr;
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info->chip.IO_ADDR_W = vaddr;
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info->chip.chip_delay = 0;
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info->chip.select_chip = nand_davinci_select_chip;
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/* options such as NAND_USE_FLASH_BBT or 16-bit widths */
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info->chip.options = pdata ? pdata->options : 0;
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info->ioaddr = (uint32_t __force) vaddr;
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info->current_cs = info->ioaddr;
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info->core_chipsel = pdev->id;
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info->mask_chipsel = pdata->mask_chipsel;
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/* use nandboot-capable ALE/CLE masks by default */
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if (pdata && pdata->mask_ale)
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info->mask_ale = pdata->mask_cle;
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else
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info->mask_ale = MASK_ALE;
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if (pdata && pdata->mask_cle)
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info->mask_cle = pdata->mask_cle;
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else
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info->mask_cle = MASK_CLE;
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/* Set address of hardware control function */
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info->chip.cmd_ctrl = nand_davinci_hwcontrol;
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info->chip.dev_ready = nand_davinci_dev_ready;
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/* Speed up buffer I/O */
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info->chip.read_buf = nand_davinci_read_buf;
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info->chip.write_buf = nand_davinci_write_buf;
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/* use board-specific ECC config; else, the best available */
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if (pdata)
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ecc_mode = pdata->ecc_mode;
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else
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ecc_mode = NAND_ECC_HW;
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switch (ecc_mode) {
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case NAND_ECC_NONE:
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case NAND_ECC_SOFT:
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break;
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case NAND_ECC_HW:
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info->chip.ecc.calculate = nand_davinci_calculate_1bit;
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info->chip.ecc.correct = nand_davinci_correct_1bit;
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info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
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info->chip.ecc.size = 512;
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info->chip.ecc.bytes = 3;
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break;
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case NAND_ECC_HW_SYNDROME:
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/* FIXME implement */
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info->chip.ecc.size = 512;
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info->chip.ecc.bytes = 10;
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dev_warn(&pdev->dev, "4-bit ECC nyet supported\n");
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/* FALL THROUGH */
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default:
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ret = -EINVAL;
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goto err_ecc;
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}
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info->chip.ecc.mode = ecc_mode;
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info->clk = clk_get(&pdev->dev, "AEMIFCLK");
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if (IS_ERR(info->clk)) {
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ret = PTR_ERR(info->clk);
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dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
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goto err_clk;
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}
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ret = clk_enable(info->clk);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
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goto err_clk_enable;
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}
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/* EMIF timings should normally be set by the boot loader,
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* especially after boot-from-NAND. The *only* reason to
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* have this special casing for the DM6446 EVM is to work
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* with boot-from-NOR ... with CS0 manually re-jumpered
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* (after startup) so it addresses the NAND flash, not NOR.
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* Even for dev boards, that's unusually rude...
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*/
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if (machine_is_davinci_evm())
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nand_dm6446evm_flash_init(info);
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spin_lock_irq(&davinci_nand_lock);
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/* put CSxNAND into NAND mode */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val |= BIT(info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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spin_unlock_irq(&davinci_nand_lock);
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/* Scan to find existence of the device(s) */
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ret = nand_scan(&info->mtd, pdata->mask_chipsel ? 2 : 1);
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if (ret < 0) {
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dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
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goto err_scan;
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}
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if (mtd_has_partitions()) {
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struct mtd_partition *mtd_parts = NULL;
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int mtd_parts_nb = 0;
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if (mtd_has_cmdlinepart()) {
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static const char *probes[] __initconst =
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{ "cmdlinepart", NULL };
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const char *master_name;
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/* Set info->mtd.name = 0 temporarily */
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master_name = info->mtd.name;
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info->mtd.name = (char *)0;
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/* info->mtd.name == 0, means: don't bother checking
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<mtd-id> */
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mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
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&mtd_parts, 0);
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/* Restore info->mtd.name */
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info->mtd.name = master_name;
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}
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if (mtd_parts_nb <= 0 && pdata) {
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mtd_parts = pdata->parts;
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mtd_parts_nb = pdata->nr_parts;
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}
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/* Register any partitions */
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if (mtd_parts_nb > 0) {
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ret = add_mtd_partitions(&info->mtd,
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mtd_parts, mtd_parts_nb);
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if (ret == 0)
|
|
info->partitioned = true;
|
|
}
|
|
|
|
} else if (pdata && pdata->nr_parts) {
|
|
dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
|
|
pdata->nr_parts, info->mtd.name);
|
|
}
|
|
|
|
/* If there's no partition info, just package the whole chip
|
|
* as a single MTD device.
|
|
*/
|
|
if (!info->partitioned)
|
|
ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
|
|
|
|
if (ret < 0)
|
|
goto err_scan;
|
|
|
|
val = davinci_nand_readl(info, NRCSR_OFFSET);
|
|
dev_info(&pdev->dev, "controller rev. %d.%d\n",
|
|
(val >> 8) & 0xff, val & 0xff);
|
|
|
|
return 0;
|
|
|
|
err_scan:
|
|
clk_disable(info->clk);
|
|
|
|
err_clk_enable:
|
|
clk_put(info->clk);
|
|
|
|
err_ecc:
|
|
err_clk:
|
|
err_ioremap:
|
|
if (base)
|
|
iounmap(base);
|
|
if (vaddr)
|
|
iounmap(vaddr);
|
|
|
|
err_nomem:
|
|
kfree(info);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit nand_davinci_remove(struct platform_device *pdev)
|
|
{
|
|
struct davinci_nand_info *info = platform_get_drvdata(pdev);
|
|
int status;
|
|
|
|
if (mtd_has_partitions() && info->partitioned)
|
|
status = del_mtd_partitions(&info->mtd);
|
|
else
|
|
status = del_mtd_device(&info->mtd);
|
|
|
|
iounmap(info->base);
|
|
iounmap(info->vaddr);
|
|
|
|
nand_release(&info->mtd);
|
|
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
|
|
kfree(info);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver nand_davinci_driver = {
|
|
.remove = __exit_p(nand_davinci_remove),
|
|
.driver = {
|
|
.name = "davinci_nand",
|
|
},
|
|
};
|
|
MODULE_ALIAS("platform:davinci_nand");
|
|
|
|
static int __init nand_davinci_init(void)
|
|
{
|
|
return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
|
|
}
|
|
module_init(nand_davinci_init);
|
|
|
|
static void __exit nand_davinci_exit(void)
|
|
{
|
|
platform_driver_unregister(&nand_davinci_driver);
|
|
}
|
|
module_exit(nand_davinci_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_DESCRIPTION("Davinci NAND flash driver");
|
|
|