288 lines
9.1 KiB
C
288 lines
9.1 KiB
C
#ifndef _ASM_IA64_SYSTEM_H
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#define _ASM_IA64_SYSTEM_H
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/*
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* System defines. Note that this is included both from .c and .S
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* files, so it does only defines, not any C code. This is based
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* on information published in the Processor Abstraction Layer
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* and the System Abstraction Layer manual.
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*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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*/
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#include <linux/config.h>
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#include <asm/kregs.h>
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#include <asm/page.h>
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#include <asm/pal.h>
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#include <asm/percpu.h>
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#define GATE_ADDR __IA64_UL_CONST(0xa000000000000000)
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/*
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* 0xa000000000000000+2*PERCPU_PAGE_SIZE
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* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
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*/
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#define KERNEL_START __IA64_UL_CONST(0xa000000100000000)
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#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
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#ifndef __ASSEMBLY__
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#include <linux/kernel.h>
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#include <linux/types.h>
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struct pci_vector_struct {
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__u16 segment; /* PCI Segment number */
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__u16 bus; /* PCI Bus number */
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__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
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__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
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__u32 irq; /* IRQ assigned */
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};
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extern struct ia64_boot_param {
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__u64 command_line; /* physical address of command line arguments */
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__u64 efi_systab; /* physical address of EFI system table */
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__u64 efi_memmap; /* physical address of EFI memory map */
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__u64 efi_memmap_size; /* size of EFI memory map */
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__u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
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__u32 efi_memdesc_version; /* memory descriptor version */
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struct {
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__u16 num_cols; /* number of columns on console output device */
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__u16 num_rows; /* number of rows on console output device */
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__u16 orig_x; /* cursor's x position */
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__u16 orig_y; /* cursor's y position */
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} console_info;
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__u64 fpswa; /* physical address of the fpswa interface */
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__u64 initrd_start;
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__u64 initrd_size;
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} *ia64_boot_param;
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/*
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* Macros to force memory ordering. In these descriptions, "previous"
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* and "subsequent" refer to program order; "visible" means that all
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* architecturally visible effects of a memory access have occurred
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* (at a minimum, this means the memory has been read or written).
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*
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* wmb(): Guarantees that all preceding stores to memory-
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* like regions are visible before any subsequent
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* stores and that all following stores will be
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* visible only after all previous stores.
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* rmb(): Like wmb(), but for reads.
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* mb(): wmb()/rmb() combo, i.e., all previous memory
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* accesses are visible before all subsequent
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* accesses and vice versa. This is also known as
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* a "fence."
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*
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* Note: "mb()" and its variants cannot be used as a fence to order
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* accesses to memory mapped I/O registers. For that, mf.a needs to
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* be used. However, we don't want to always use mf.a because (a)
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* it's (presumably) much slower than mf and (b) mf.a is supported for
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* sequential memory pages only.
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*/
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#define mb() ia64_mf()
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_SMP
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# define smp_mb() mb()
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# define smp_rmb() rmb()
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# define smp_wmb() wmb()
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# define smp_read_barrier_depends() read_barrier_depends()
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#else
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# define smp_mb() barrier()
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# define smp_rmb() barrier()
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# define smp_wmb() barrier()
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# define smp_read_barrier_depends() do { } while(0)
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#endif
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/*
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* XXX check on these---I suspect what Linus really wants here is
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* acquire vs release semantics but we can't discuss this stuff with
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* Linus just yet. Grrr...
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*/
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#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
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#define set_wmb(var, value) do { (var) = (value); mb(); } while (0)
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#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
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/*
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* The group barrier in front of the rsm & ssm are necessary to ensure
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* that none of the previous instructions in the same group are
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* affected by the rsm/ssm.
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*/
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/* For spinlocks etc */
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/*
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* - clearing psr.i is implicitly serialized (visible by next insn)
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* - setting psr.i requires data serialization
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* - we need a stop-bit before reading PSR because we sometimes
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* write a floating-point register right before reading the PSR
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* and that writes to PSR.mfl
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*/
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#define __local_irq_save(x) \
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do { \
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ia64_stop(); \
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(x) = ia64_getreg(_IA64_REG_PSR); \
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ia64_stop(); \
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ia64_rsm(IA64_PSR_I); \
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} while (0)
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#define __local_irq_disable() \
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do { \
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ia64_stop(); \
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ia64_rsm(IA64_PSR_I); \
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} while (0)
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#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
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#ifdef CONFIG_IA64_DEBUG_IRQ
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extern unsigned long last_cli_ip;
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# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
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# define local_irq_save(x) \
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do { \
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unsigned long psr; \
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\
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__local_irq_save(psr); \
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if (psr & IA64_PSR_I) \
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__save_ip(); \
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(x) = psr; \
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} while (0)
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# define local_irq_disable() do { unsigned long x; local_irq_save(x); } while (0)
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# define local_irq_restore(x) \
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do { \
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unsigned long old_psr, psr = (x); \
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\
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local_save_flags(old_psr); \
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__local_irq_restore(psr); \
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if ((old_psr & IA64_PSR_I) && !(psr & IA64_PSR_I)) \
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__save_ip(); \
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} while (0)
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#else /* !CONFIG_IA64_DEBUG_IRQ */
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# define local_irq_save(x) __local_irq_save(x)
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# define local_irq_disable() __local_irq_disable()
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# define local_irq_restore(x) __local_irq_restore(x)
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#endif /* !CONFIG_IA64_DEBUG_IRQ */
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#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
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#define local_save_flags(flags) ({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); })
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#define irqs_disabled() \
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({ \
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unsigned long __ia64_id_flags; \
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local_save_flags(__ia64_id_flags); \
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(__ia64_id_flags & IA64_PSR_I) == 0; \
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})
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#ifdef __KERNEL__
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#ifdef CONFIG_IA32_SUPPORT
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# define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
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#else
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# define IS_IA32_PROCESS(regs) 0
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struct task_struct;
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static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
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static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
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#endif
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/*
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* Context switch from one thread to another. If the two threads have
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* different address spaces, schedule() has already taken care of
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* switching to the new address space by calling switch_mm().
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*
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* Disabling access to the fph partition and the debug-register
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* context switch MUST be done before calling ia64_switch_to() since a
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* newly created thread returns directly to
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* ia64_ret_from_syscall_clear_r8.
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*/
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extern struct task_struct *ia64_switch_to (void *next_task);
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struct task_struct;
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extern void ia64_save_extra (struct task_struct *task);
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extern void ia64_load_extra (struct task_struct *task);
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#ifdef CONFIG_PERFMON
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DECLARE_PER_CPU(unsigned long, pfm_syst_info);
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# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
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#else
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# define PERFMON_IS_SYSWIDE() (0)
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#endif
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#define IA64_HAS_EXTRA_STATE(t) \
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((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
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|| IS_IA32_PROCESS(ia64_task_regs(t)) || PERFMON_IS_SYSWIDE())
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#define __switch_to(prev,next,last) do { \
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if (IA64_HAS_EXTRA_STATE(prev)) \
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ia64_save_extra(prev); \
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if (IA64_HAS_EXTRA_STATE(next)) \
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ia64_load_extra(next); \
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ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
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(last) = ia64_switch_to((next)); \
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} while (0)
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#ifdef CONFIG_SMP
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/*
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* In the SMP case, we save the fph state when context-switching away from a thread that
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* modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
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* pick up the state from task->thread.fph, avoiding the complication of having to fetch
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* the latest fph state from another CPU. In other words: eager save, lazy restore.
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*/
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# define switch_to(prev,next,last) do { \
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if (ia64_psr(ia64_task_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
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ia64_psr(ia64_task_regs(prev))->mfh = 0; \
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(prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
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__ia64_save_fpu((prev)->thread.fph); \
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} \
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__switch_to(prev, next, last); \
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} while (0)
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#else
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# define switch_to(prev,next,last) __switch_to(prev, next, last)
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#endif
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/*
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* On IA-64, we don't want to hold the runqueue's lock during the low-level context-switch,
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* because that could cause a deadlock. Here is an example by Erich Focht:
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*
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* Example:
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* CPU#0:
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* schedule()
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* -> spin_lock_irq(&rq->lock)
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* -> context_switch()
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* -> wrap_mmu_context()
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* -> read_lock(&tasklist_lock)
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*
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* CPU#1:
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* sys_wait4() or release_task() or forget_original_parent()
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* -> write_lock(&tasklist_lock)
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* -> do_notify_parent()
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* -> wake_up_parent()
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* -> try_to_wake_up()
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* -> spin_lock_irq(&parent_rq->lock)
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*
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* If the parent's rq happens to be on CPU#0, we'll wait for the rq->lock
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* of that CPU which will not be released, because there we wait for the
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* tasklist_lock to become available.
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*/
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
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void cpu_idle_wait(void);
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_IA64_SYSTEM_H */
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