424 lines
13 KiB
C
424 lines
13 KiB
C
/*
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* Interrupt controller support for Marvell's MV64360.
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*
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* Author: Rabeeh Khoury <rabeeh@galileo.co.il>
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* Based on MV64360 PIC written by
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* Chris Zankel <chris@mvista.com>
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* Mark A. Greer <mgreer@mvista.com>
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*
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* Copyright 2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* This file contains the specific functions to support the MV64360
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* interrupt controller.
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*
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* The MV64360 has two main interrupt registers (high and low) that
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* summarizes the interrupts generated by the units of the MV64360.
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* Each bit is assigned to an interrupt number, where the low register
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* are assigned from IRQ0 to IRQ31 and the high cause register
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* from IRQ32 to IRQ63
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* The GPP (General Purpose Pins) interrupts are assigned from IRQ64 (GPP0)
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* to IRQ95 (GPP31).
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* get_irq() returns the lowest interrupt number that is currently asserted.
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*
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* Note:
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* - This driver does not initialize the GPP when used as an interrupt
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* input.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/mv64x60.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_IRQ_ALL_CPUS
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#error "The mv64360 does not support distribution of IRQs on all CPUs"
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#endif
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/* ========================== forward declaration ========================== */
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static void mv64360_unmask_irq(unsigned int);
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static void mv64360_mask_irq(unsigned int);
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static irqreturn_t mv64360_cpu_error_int_handler(int, void *);
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static irqreturn_t mv64360_sram_error_int_handler(int, void *);
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static irqreturn_t mv64360_pci_error_int_handler(int, void *);
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/* ========================== local declarations =========================== */
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struct hw_interrupt_type mv64360_pic = {
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.typename = " mv64360 ",
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.enable = mv64360_unmask_irq,
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.disable = mv64360_mask_irq,
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.ack = mv64360_mask_irq,
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.end = mv64360_unmask_irq,
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};
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#define CPU_INTR_STR "mv64360 cpu interface error"
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#define SRAM_INTR_STR "mv64360 internal sram error"
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#define PCI0_INTR_STR "mv64360 pci 0 error"
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#define PCI1_INTR_STR "mv64360 pci 1 error"
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static struct mv64x60_handle bh;
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u32 mv64360_irq_base = 0; /* MV64360 handles the next 96 IRQs from here */
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/* mv64360_init_irq()
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*
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* This function initializes the interrupt controller. It assigns
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* all interrupts from IRQ0 to IRQ95 to the mv64360 interrupt controller.
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*
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* Input Variable(s):
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* None.
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*
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* Outpu. Variable(s):
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* None.
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*
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* Returns:
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* void
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*
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* Note:
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* We register all GPP inputs as interrupt source, but disable them.
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*/
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void __init
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mv64360_init_irq(void)
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{
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int i;
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if (ppc_md.progress)
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ppc_md.progress("mv64360_init_irq: enter", 0x0);
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bh.v_base = mv64x60_get_bridge_vbase();
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ppc_cached_irq_mask[0] = 0;
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ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
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ppc_cached_irq_mask[2] = 0;
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/* disable all interrupts and clear current interrupts */
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mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
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mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,ppc_cached_irq_mask[0]);
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,ppc_cached_irq_mask[1]);
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/* All interrupts are level interrupts */
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for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) {
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irq_desc[i].status |= IRQ_LEVEL;
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irq_desc[i].chip = &mv64360_pic;
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}
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if (ppc_md.progress)
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ppc_md.progress("mv64360_init_irq: exit", 0x0);
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}
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/* mv64360_get_irq()
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*
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* This function returns the lowest interrupt number of all interrupts that
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* are currently asserted.
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*
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* Output Variable(s):
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* None.
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*
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* Returns:
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* int <interrupt number> or -2 (bogus interrupt)
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*
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*/
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int
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mv64360_get_irq(void)
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{
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int irq;
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int irq_gpp;
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#ifdef CONFIG_SMP
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/*
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* Second CPU gets only doorbell (message) interrupts.
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* The doorbell interrupt is BIT28 in the main interrupt low cause reg.
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*/
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int cpu_nr = smp_processor_id();
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if (cpu_nr == 1) {
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if (!(mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO) &
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(1 << MV64x60_IRQ_DOORBELL)))
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return -1;
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return mv64360_irq_base + MV64x60_IRQ_DOORBELL;
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}
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#endif
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irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO);
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irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
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if (irq == -1) {
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irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
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irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
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if (irq == -1)
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irq = -2; /* bogus interrupt, should never happen */
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else {
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if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
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irq_gpp = mv64x60_read(&bh,
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MV64x60_GPP_INTR_CAUSE);
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irq_gpp = __ilog2(irq_gpp &
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ppc_cached_irq_mask[2]);
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if (irq_gpp == -1)
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irq = -2;
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else {
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irq = irq_gpp + 64;
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mv64x60_write(&bh,
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MV64x60_GPP_INTR_CAUSE,
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~(1 << (irq - 64)));
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}
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}
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else
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irq += 32;
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}
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}
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(void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
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if (irq < 0)
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return (irq);
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else
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return (mv64360_irq_base + irq);
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}
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/* mv64360_unmask_irq()
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*
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* This function enables an interrupt.
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*
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* Input Variable(s):
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* unsigned int interrupt number (IRQ0...IRQ95).
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*
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* Output Variable(s):
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* None.
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*
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* Returns:
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* void
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*/
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static void
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mv64360_unmask_irq(unsigned int irq)
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{
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#ifdef CONFIG_SMP
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/* second CPU gets only doorbell interrupts */
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if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) {
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mv64x60_set_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO,
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(1 << MV64x60_IRQ_DOORBELL));
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return;
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}
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#endif
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irq -= mv64360_irq_base;
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if (irq > 31) {
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if (irq > 63) /* unmask GPP irq */
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mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
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ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
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else /* mask high interrupt register */
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,
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ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
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}
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else /* mask low interrupt register */
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,
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ppc_cached_irq_mask[0] |= (1 << irq));
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(void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
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return;
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}
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/* mv64360_mask_irq()
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*
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* This function disables the requested interrupt.
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*
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* Input Variable(s):
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* unsigned int interrupt number (IRQ0...IRQ95).
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*
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* Output Variable(s):
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* None.
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*
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* Returns:
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* void
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*/
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static void
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mv64360_mask_irq(unsigned int irq)
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{
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#ifdef CONFIG_SMP
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if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) {
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mv64x60_clr_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO,
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(1 << MV64x60_IRQ_DOORBELL));
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return;
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}
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#endif
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irq -= mv64360_irq_base;
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if (irq > 31) {
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if (irq > 63) /* mask GPP irq */
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mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
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ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
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else /* mask high interrupt register */
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,
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ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
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}
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else /* mask low interrupt register */
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mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,
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ppc_cached_irq_mask[0] &= ~(1 << irq));
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(void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
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return;
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}
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static irqreturn_t
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mv64360_cpu_error_int_handler(int irq, void *dev_id)
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{
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printk(KERN_ERR "mv64360_cpu_error_int_handler: %s 0x%08x\n",
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"Error on CPU interface - Cause regiser",
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mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
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printk(KERN_ERR "\tCPU error register dump:\n");
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printk(KERN_ERR "\tAddress low 0x%08x\n",
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mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
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printk(KERN_ERR "\tAddress high 0x%08x\n",
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mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
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printk(KERN_ERR "\tData low 0x%08x\n",
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mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
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printk(KERN_ERR "\tData high 0x%08x\n",
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mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
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printk(KERN_ERR "\tParity 0x%08x\n",
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mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
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mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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mv64360_sram_error_int_handler(int irq, void *dev_id)
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{
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printk(KERN_ERR "mv64360_sram_error_int_handler: %s 0x%08x\n",
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"Error in internal SRAM - Cause register",
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mv64x60_read(&bh, MV64360_SRAM_ERR_CAUSE));
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printk(KERN_ERR "\tSRAM error register dump:\n");
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printk(KERN_ERR "\tAddress Low 0x%08x\n",
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mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_LO));
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printk(KERN_ERR "\tAddress High 0x%08x\n",
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mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_HI));
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printk(KERN_ERR "\tData Low 0x%08x\n",
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mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_LO));
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printk(KERN_ERR "\tData High 0x%08x\n",
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mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_HI));
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printk(KERN_ERR "\tParity 0x%08x\n",
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mv64x60_read(&bh, MV64360_SRAM_ERR_PARITY));
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mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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mv64360_pci_error_int_handler(int irq, void *dev_id)
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{
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u32 val;
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unsigned int pci_bus = (unsigned int)dev_id;
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if (pci_bus == 0) { /* Error on PCI 0 */
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val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
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printk(KERN_ERR "%s: Error in PCI %d Interface\n",
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"mv64360_pci_error_int_handler", pci_bus);
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printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
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printk(KERN_ERR "\tCause register 0x%08x\n", val);
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printk(KERN_ERR "\tAddress Low 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
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printk(KERN_ERR "\tAddress High 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
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printk(KERN_ERR "\tAttribute 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
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printk(KERN_ERR "\tCommand 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
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mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
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}
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if (pci_bus == 1) { /* Error on PCI 1 */
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val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
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printk(KERN_ERR "%s: Error in PCI %d Interface\n",
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"mv64360_pci_error_int_handler", pci_bus);
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printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
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printk(KERN_ERR "\tCause register 0x%08x\n", val);
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printk(KERN_ERR "\tAddress Low 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
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printk(KERN_ERR "\tAddress High 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
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printk(KERN_ERR "\tAttribute 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
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printk(KERN_ERR "\tCommand 0x%08x\n",
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mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
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mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
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}
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return IRQ_HANDLED;
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}
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/*
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* Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
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* errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
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* well. IOW, don't set bit 0.
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*/
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#define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24
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static int __init
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mv64360_register_hdlrs(void)
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{
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int rc;
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/* Clear old errors and register CPU interface error intr handler */
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mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
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if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base,
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mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, NULL)))
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printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
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mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
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mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
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/* Clear old errors and register internal SRAM error intr handler */
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mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
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if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base,
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mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, NULL)))
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printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
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/* Clear old errors and register PCI 0 error intr handler */
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mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
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if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base,
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mv64360_pci_error_int_handler,
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IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
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printk(KERN_WARNING "Can't register pci 0 error handler: %d",
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rc);
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mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
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mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
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/* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */
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mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK,
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mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL);
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/* Clear old errors and register PCI 1 error intr handler */
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mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
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if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base,
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mv64360_pci_error_int_handler,
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IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
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printk(KERN_WARNING "Can't register pci 1 error handler: %d",
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rc);
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mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
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mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
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/* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */
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mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK,
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mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL);
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return 0;
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}
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arch_initcall(mv64360_register_hdlrs);
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