310 lines
9.6 KiB
C
310 lines
9.6 KiB
C
/*
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* init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
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*
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* Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
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*
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* Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
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* this file has functions to:
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* - scan the PCI very early on boot for all OHCI 1394-compliant controllers
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* - reset and initialize them and make them join the IEEE1394 bus and
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* - enable physical DMA on them to allow remote debugging
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*
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* All code and data is marked as __init and __initdata, respective as
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* during boot, all OHCI1394 controllers may be claimed by the firewire
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* stack and at this point, this code should not touch them anymore.
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*
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* To use physical DMA after the initialization of the firewire stack,
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* be sure that the stack enables it and (re-)attach after the bus reset
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* which may be caused by the firewire stack initialization.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pci.h> /* for PCI defines */
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#include <linux/string.h>
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#include <asm/pci-direct.h> /* for direct PCI config space access */
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#include <asm/fixmap.h>
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#include <linux/init_ohci1394_dma.h>
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#include "ohci.h"
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int __initdata init_ohci1394_dma_early;
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struct ohci {
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void __iomem *registers;
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};
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static inline void reg_write(const struct ohci *ohci, int offset, u32 data)
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{
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writel(data, ohci->registers + offset);
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}
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static inline u32 reg_read(const struct ohci *ohci, int offset)
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{
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return readl(ohci->registers + offset);
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}
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#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
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/* Reads a PHY register of an OHCI-1394 controller */
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static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr)
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{
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int i;
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u32 r;
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reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
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for (i = 0; i < OHCI_LOOP_COUNT; i++) {
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if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
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break;
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mdelay(1);
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}
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r = reg_read(ohci, OHCI1394_PhyControl);
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return (r & 0x00ff0000) >> 16;
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}
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/* Writes to a PHY register of an OHCI-1394 controller */
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static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data)
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{
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int i;
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reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
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for (i = 0; i < OHCI_LOOP_COUNT; i++) {
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if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000))
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break;
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mdelay(1);
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}
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}
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/* Resets an OHCI-1394 controller (for sane state before initialization) */
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static inline void __init init_ohci1394_soft_reset(struct ohci *ohci)
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{
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int i;
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reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
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for (i = 0; i < OHCI_LOOP_COUNT; i++) {
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if (!(reg_read(ohci, OHCI1394_HCControlSet)
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& OHCI1394_HCControl_softReset))
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break;
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mdelay(1);
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}
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}
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#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
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#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
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#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
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/* Basic OHCI-1394 register and port inititalization */
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static inline void __init init_ohci1394_initialize(struct ohci *ohci)
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{
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u32 bus_options;
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int num_ports, i;
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/* Put some defaults to these undefined bus options */
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bus_options = reg_read(ohci, OHCI1394_BusOptions);
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bus_options |= 0x60000000; /* Enable CMC and ISC */
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bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
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bus_options &= ~0x18000000; /* Disable PMC and BMC */
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reg_write(ohci, OHCI1394_BusOptions, bus_options);
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/* Set the bus number */
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reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
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/* Enable posted writes */
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reg_write(ohci, OHCI1394_HCControlSet,
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OHCI1394_HCControl_postedWriteEnable);
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/* Clear link control register */
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reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
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/* enable phys */
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reg_write(ohci, OHCI1394_LinkControlSet,
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OHCI1394_LinkControl_rcvPhyPkt);
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/* Don't accept phy packets into AR request context */
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reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
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/* Clear the Isochonouys interrupt masks */
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reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
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reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
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reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
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reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
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/* Accept asyncronous transfer requests from all nodes for now */
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reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
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/* Specify asyncronous transfer retries */
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reg_write(ohci, OHCI1394_ATRetries,
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OHCI1394_MAX_AT_REQ_RETRIES |
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(OHCI1394_MAX_AT_RESP_RETRIES<<4) |
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(OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
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/* We don't want hardware swapping */
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reg_write(ohci, OHCI1394_HCControlClear,
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OHCI1394_HCControl_noByteSwapData);
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/* Enable link */
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reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
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/* If anything is connected to a port, make sure it is enabled */
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num_ports = get_phy_reg(ohci, 2) & 0xf;
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for (i = 0; i < num_ports; i++) {
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unsigned int status;
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set_phy_reg(ohci, 7, i);
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status = get_phy_reg(ohci, 8);
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if (status & 0x20)
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set_phy_reg(ohci, 8, status & ~1);
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}
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}
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/**
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* init_ohci1394_wait_for_busresets - wait until bus resets are completed
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*
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* OHCI1394 initialization itself and any device going on- or offline
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* and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
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* specifies that physical DMA is disabled on each bus reset and it
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* has to be enabled after each bus reset when needed. We resort
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* to polling here because on early boot, we have no interrupts.
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*/
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static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci)
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{
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int i, events;
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for (i = 0; i < 9; i++) {
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mdelay(200);
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events = reg_read(ohci, OHCI1394_IntEventSet);
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if (events & OHCI1394_busReset)
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reg_write(ohci, OHCI1394_IntEventClear,
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OHCI1394_busReset);
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}
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}
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/**
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* init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
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* This enables remote DMA access over IEEE1394 from every host for the low
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* 4GB of address space. DMA accesses above 4GB are not available currently.
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*/
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static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci)
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{
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reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
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reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
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reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
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}
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/**
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* init_ohci1394_reset_and_init_dma - init controller and enable DMA
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* This initializes the given controller and enables physical DMA engine in it.
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*/
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static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci)
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{
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/* Start off with a soft reset, clears everything to a sane state. */
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init_ohci1394_soft_reset(ohci);
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/* Accessing some registers without LPS enabled may cause lock up */
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reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
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/* Disable and clear interrupts */
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reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
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reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
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mdelay(50); /* Wait 50msec to make sure we have full link enabled */
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init_ohci1394_initialize(ohci);
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/*
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* The initialization causes at least one IEEE1394 bus reset. Enabling
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* physical DMA only works *after* *all* bus resets have calmed down:
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*/
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init_ohci1394_wait_for_busresets(ohci);
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/* We had to wait and do this now if we want to debug early problems */
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init_ohci1394_enable_physical_dma(ohci);
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}
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/**
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* init_ohci1394_controller - Map the registers of the controller and init DMA
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* This maps the registers of the specified controller and initializes it
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*/
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static inline void __init init_ohci1394_controller(int num, int slot, int func)
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{
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unsigned long ohci_base;
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struct ohci ohci;
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printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
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" at %02x:%02x.%x\n", num, slot, func);
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ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
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& PCI_BASE_ADDRESS_MEM_MASK;
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set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
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ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
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init_ohci1394_reset_and_init_dma(&ohci);
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}
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/**
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* debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them
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* Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
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*/
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void __init init_ohci1394_dma_on_all_controllers(void)
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{
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int num, slot, func;
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u32 class;
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if (!early_pci_allowed())
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return;
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/* Poor man's PCI discovery, the only thing we can do at early boot */
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for (num = 0; num < 32; num++) {
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for (slot = 0; slot < 32; slot++) {
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for (func = 0; func < 8; func++) {
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class = read_pci_config(num, slot, func,
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PCI_CLASS_REVISION);
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if (class == 0xffffffff)
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continue; /* No device at this func */
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if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
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continue; /* Not an OHCI-1394 device */
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init_ohci1394_controller(num, slot, func);
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break; /* Assume one controller per device */
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}
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}
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}
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printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
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}
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/**
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* setup_init_ohci1394_early - enables early OHCI1394 DMA initialization
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*/
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static int __init setup_ohci1394_dma(char *opt)
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{
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if (!strcmp(opt, "early"))
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init_ohci1394_dma_early = 1;
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return 0;
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}
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/* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
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early_param("ohci1394_dma", setup_ohci1394_dma);
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