559 lines
15 KiB
C
559 lines
15 KiB
C
/*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/uaccess.h>
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extern void sb1_dma_init(void);
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/* These are probed at ld_mmu time */
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static unsigned long icache_size;
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static unsigned long dcache_size;
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static unsigned short icache_line_size;
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static unsigned short dcache_line_size;
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static unsigned int icache_index_mask;
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static unsigned int dcache_index_mask;
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static unsigned short icache_assoc;
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static unsigned short dcache_assoc;
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static unsigned short icache_sets;
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static unsigned short dcache_sets;
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static unsigned int icache_range_cutoff;
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static unsigned int dcache_range_cutoff;
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/*
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* The dcache is fully coherent to the system, with one
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* big caveat: the instruction stream. In other words,
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* if we miss in the icache, and have dirty data in the
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* L1 dcache, then we'll go out to memory (or the L2) and
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* get the not-as-recent data.
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*
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* So the only time we have to flush the dcache is when
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* we're flushing the icache. Since the L2 is fully
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* coherent to everything, including I/O, we never have
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* to flush it
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*/
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#define cache_set_op(op, addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips64\n\t \n" \
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" cache %0, (0<<13)(%1) \n" \
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" cache %0, (1<<13)(%1) \n" \
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" cache %0, (2<<13)(%1) \n" \
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" cache %0, (3<<13)(%1) \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "r" (addr))
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#define sync() \
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__asm__ __volatile( \
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" .set mips64\n\t \n" \
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" sync \n" \
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" .set mips0")
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#define mispredict() \
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__asm__ __volatile__( \
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" bnezl $0, 1f \n" /* Force mispredict */ \
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"1: \n");
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/*
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* Writeback and invalidate the entire dcache
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*/
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static inline void __sb1_writeback_inv_dcache_all(void)
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{
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unsigned long addr = 0;
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while (addr < dcache_line_size * dcache_sets) {
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cache_set_op(Index_Writeback_Inv_D, addr);
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addr += dcache_line_size;
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}
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}
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/*
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* Writeback and invalidate a range of the dcache. The addresses are
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* virtual, and since we're using index ops and bit 12 is part of both
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* the virtual frame and physical index, we have to clear both sets
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* (bit 12 set and cleared).
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*/
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static inline void __sb1_writeback_inv_dcache_range(unsigned long start,
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unsigned long end)
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{
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unsigned long index;
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start &= ~(dcache_line_size - 1);
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end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
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while (start != end) {
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index = start & dcache_index_mask;
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cache_set_op(Index_Writeback_Inv_D, index);
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cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12));
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start += dcache_line_size;
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}
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sync();
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}
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/*
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* Writeback and invalidate a range of the dcache. With physical
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* addresseses, we don't have to worry about possible bit 12 aliasing.
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* XXXKW is it worth turning on KX and using hit ops with xkphys?
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*/
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static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(dcache_line_size - 1);
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end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask);
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start += dcache_line_size;
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}
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sync();
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}
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/*
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* Invalidate the entire icache
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*/
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static inline void __sb1_flush_icache_all(void)
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{
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unsigned long addr = 0;
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while (addr < icache_line_size * icache_sets) {
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cache_set_op(Index_Invalidate_I, addr);
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addr += icache_line_size;
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}
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}
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/*
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* Flush the icache for a given physical page. Need to writeback the
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* dcache first, then invalidate the icache. If the page isn't
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* executable, nothing is required.
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*/
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static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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{
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int cpu = smp_processor_id();
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#ifndef CONFIG_SMP
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if (!(vma->vm_flags & VM_EXEC))
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return;
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#endif
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__sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
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/*
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* Bumping the ASID is probably cheaper than the flush ...
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*/
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if (cpu_context(cpu, vma->vm_mm) != 0)
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drop_mmu_context(vma->vm_mm, cpu);
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}
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#ifdef CONFIG_SMP
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struct flush_cache_page_args {
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struct vm_area_struct *vma;
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unsigned long addr;
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unsigned long pfn;
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};
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static void sb1_flush_cache_page_ipi(void *info)
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{
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struct flush_cache_page_args *args = info;
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local_sb1_flush_cache_page(args->vma, args->addr, args->pfn);
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}
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/* Dirty dcache could be on another CPU, so do the IPIs */
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static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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{
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struct flush_cache_page_args args;
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if (!(vma->vm_flags & VM_EXEC))
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return;
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addr &= PAGE_MASK;
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args.vma = vma;
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args.addr = addr;
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args.pfn = pfn;
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on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
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}
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#else
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void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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__attribute__((alias("local_sb1_flush_cache_page")));
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#endif
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/*
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* Invalidate a range of the icache. The addresses are virtual, and
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* the cache is virtually indexed and tagged. However, we don't
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* necessarily have the right ASID context, so use index ops instead
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* of hit ops.
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*/
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static inline void __sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(icache_line_size - 1);
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end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Invalidate_I, start & icache_index_mask);
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start += icache_line_size;
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}
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mispredict();
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sync();
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}
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/*
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* Invalidate all caches on this CPU
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*/
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static void __attribute_used__ local_sb1___flush_cache_all(void)
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{
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__sb1_writeback_inv_dcache_all();
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__sb1_flush_icache_all();
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}
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#ifdef CONFIG_SMP
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void sb1___flush_cache_all_ipi(void *ignored)
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__attribute__((alias("local_sb1___flush_cache_all")));
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static void sb1___flush_cache_all(void)
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{
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on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
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}
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#else
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void sb1___flush_cache_all(void)
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__attribute__((alias("local_sb1___flush_cache_all")));
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#endif
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/*
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* When flushing a range in the icache, we have to first writeback
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* the dcache for the same range, so new ifetches will see any
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* data that was dirty in the dcache.
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*
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* The start/end arguments are Kseg addresses (possibly mapped Kseg).
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*/
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static void local_sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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/* Just wb-inv the whole dcache if the range is big enough */
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if ((end - start) > dcache_range_cutoff)
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__sb1_writeback_inv_dcache_all();
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else
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__sb1_writeback_inv_dcache_range(start, end);
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/* Just flush the whole icache if the range is big enough */
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if ((end - start) > icache_range_cutoff)
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__sb1_flush_icache_all();
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else
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__sb1_flush_icache_range(start, end);
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}
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#ifdef CONFIG_SMP
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struct flush_icache_range_args {
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unsigned long start;
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unsigned long end;
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};
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static void sb1_flush_icache_range_ipi(void *info)
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{
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struct flush_icache_range_args *args = info;
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local_sb1_flush_icache_range(args->start, args->end);
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}
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void sb1_flush_icache_range(unsigned long start, unsigned long end)
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{
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struct flush_icache_range_args args;
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args.start = start;
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args.end = end;
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on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
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}
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#else
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void sb1_flush_icache_range(unsigned long start, unsigned long end)
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__attribute__((alias("local_sb1_flush_icache_range")));
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#endif
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/*
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* Flush the icache for a given physical page. Need to writeback the
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* dcache first, then invalidate the icache. If the page isn't
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* executable, nothing is required.
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*/
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static void local_sb1_flush_icache_page(struct vm_area_struct *vma,
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struct page *page)
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{
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unsigned long start;
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int cpu = smp_processor_id();
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#ifndef CONFIG_SMP
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if (!(vma->vm_flags & VM_EXEC))
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return;
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#endif
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/* Need to writeback any dirty data for that page, we have the PA */
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start = (unsigned long)(page-mem_map) << PAGE_SHIFT;
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__sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE);
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/*
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* If there's a context, bump the ASID (cheaper than a flush,
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* since we don't know VAs!)
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*/
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if (cpu_context(cpu, vma->vm_mm) != 0) {
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drop_mmu_context(vma->vm_mm, cpu);
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}
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}
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#ifdef CONFIG_SMP
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struct flush_icache_page_args {
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struct vm_area_struct *vma;
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struct page *page;
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};
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static void sb1_flush_icache_page_ipi(void *info)
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{
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struct flush_icache_page_args *args = info;
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local_sb1_flush_icache_page(args->vma, args->page);
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}
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/* Dirty dcache could be on another CPU, so do the IPIs */
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static void sb1_flush_icache_page(struct vm_area_struct *vma,
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struct page *page)
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{
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struct flush_icache_page_args args;
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if (!(vma->vm_flags & VM_EXEC))
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return;
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args.vma = vma;
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args.page = page;
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on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1);
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}
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#else
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void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
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__attribute__((alias("local_sb1_flush_icache_page")));
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#endif
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/*
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* A signal trampoline must fit into a single cacheline.
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*/
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static void local_sb1_flush_cache_sigtramp(unsigned long addr)
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{
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cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask);
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cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask);
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cache_set_op(Index_Invalidate_I, addr & icache_index_mask);
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mispredict();
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}
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#ifdef CONFIG_SMP
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static void sb1_flush_cache_sigtramp_ipi(void *info)
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{
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unsigned long iaddr = (unsigned long) info;
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local_sb1_flush_cache_sigtramp(iaddr);
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}
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static void sb1_flush_cache_sigtramp(unsigned long addr)
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{
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on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
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}
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#else
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void sb1_flush_cache_sigtramp(unsigned long addr)
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__attribute__((alias("local_sb1_flush_cache_sigtramp")));
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#endif
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/*
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* Anything that just flushes dcache state can be ignored, as we're always
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* coherent in dcache space. This is just a dummy function that all the
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* nop'ed routines point to
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*/
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static void sb1_nop(void)
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{
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}
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/*
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* Cache set values (from the mips64 spec)
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* 0 - 64
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* 1 - 128
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* 2 - 256
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* 3 - 512
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* 4 - 1024
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* 5 - 2048
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* 6 - 4096
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* 7 - Reserved
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*/
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static unsigned int decode_cache_sets(unsigned int config_field)
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{
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if (config_field == 7) {
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/* JDCXXX - Find a graceful way to abort. */
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return 0;
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}
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return (1<<(config_field + 6));
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}
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/*
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* Cache line size values (from the mips64 spec)
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* 0 - No cache present.
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* 1 - 4 bytes
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* 2 - 8 bytes
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* 3 - 16 bytes
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* 4 - 32 bytes
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* 5 - 64 bytes
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* 6 - 128 bytes
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* 7 - Reserved
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*/
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static unsigned int decode_cache_line_size(unsigned int config_field)
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{
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if (config_field == 0) {
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return 0;
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} else if (config_field == 7) {
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/* JDCXXX - Find a graceful way to abort. */
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return 0;
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}
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return (1<<(config_field + 1));
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}
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/*
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* Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs)
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*
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* 24:22 Icache sets per way
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* 21:19 Icache line size
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* 18:16 Icache Associativity
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* 15:13 Dcache sets per way
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* 12:10 Dcache line size
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* 9:7 Dcache Associativity
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*/
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static char *way_string[] = {
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"direct mapped", "2-way", "3-way", "4-way",
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"5-way", "6-way", "7-way", "8-way",
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};
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static __init void probe_cache_sizes(void)
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{
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u32 config1;
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config1 = read_c0_config1();
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icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7);
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dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7);
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icache_sets = decode_cache_sets((config1 >> 22) & 0x7);
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dcache_sets = decode_cache_sets((config1 >> 13) & 0x7);
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icache_assoc = ((config1 >> 16) & 0x7) + 1;
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dcache_assoc = ((config1 >> 7) & 0x7) + 1;
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icache_size = icache_line_size * icache_sets * icache_assoc;
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dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
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/* Need to remove non-index bits for index ops */
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icache_index_mask = (icache_sets - 1) * icache_line_size;
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dcache_index_mask = (dcache_sets - 1) * dcache_line_size;
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/*
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* These are for choosing range (index ops) versus all.
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* icache flushes all ways for each set, so drop icache_assoc.
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* dcache flushes all ways and each setting of bit 12 for each
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* index, so drop dcache_assoc and halve the dcache_sets.
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*/
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icache_range_cutoff = icache_sets * icache_line_size;
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dcache_range_cutoff = (dcache_sets / 2) * icache_line_size;
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printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n",
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icache_size >> 10, way_string[icache_assoc - 1],
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icache_line_size);
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printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
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dcache_size >> 10, way_string[dcache_assoc - 1],
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dcache_line_size);
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}
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/*
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* This is called from loadmmu.c. We have to set up all the
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* memory management function pointers, as well as initialize
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* the caches and tlbs
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*/
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void ld_mmu_sb1(void)
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{
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extern char except_vec2_sb1;
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extern char handle_vec2_sb1;
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/* Special cache error handler for SB1 */
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memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80);
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memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
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memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
|
|
|
|
probe_cache_sizes();
|
|
|
|
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
|
|
sb1_dma_init();
|
|
#endif
|
|
|
|
/*
|
|
* None of these are needed for the SB1 - the Dcache is
|
|
* physically indexed and tagged, so no virtual aliasing can
|
|
* occur
|
|
*/
|
|
flush_cache_range = (void *) sb1_nop;
|
|
flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
|
|
flush_cache_all = sb1_nop;
|
|
|
|
/* These routines are for Icache coherence with the Dcache */
|
|
flush_icache_range = sb1_flush_icache_range;
|
|
flush_icache_page = sb1_flush_icache_page;
|
|
flush_icache_all = __sb1_flush_icache_all; /* local only */
|
|
|
|
/* This implies an Icache flush too, so can't be nop'ed */
|
|
flush_cache_page = sb1_flush_cache_page;
|
|
|
|
flush_cache_sigtramp = sb1_flush_cache_sigtramp;
|
|
flush_data_cache_page = (void *) sb1_nop;
|
|
|
|
/* Full flush */
|
|
__flush_cache_all = sb1___flush_cache_all;
|
|
|
|
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
|
|
|
/*
|
|
* This is the only way to force the update of K0 to complete
|
|
* before subsequent instruction fetch.
|
|
*/
|
|
__asm__ __volatile__(
|
|
".set push \n"
|
|
" .set noat \n"
|
|
" .set noreorder \n"
|
|
" .set mips3 \n"
|
|
" " STR(PTR_LA) " $1, 1f \n"
|
|
" " STR(MTC0) " $1, $14 \n"
|
|
" eret \n"
|
|
"1: .set pop"
|
|
:
|
|
:
|
|
: "memory");
|
|
|
|
flush_cache_all();
|
|
}
|