68 lines
2.4 KiB
C
68 lines
2.4 KiB
C
/*
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* Copyright (C) 2002 Momentum Computer, Inc.
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* Author: Matthew Dharm, mdharm@momenco.com
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*
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* Based on work by:
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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extern asmlinkage void jaguar_handle_int(void);
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static struct irqaction cascade_mv64340 = {
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no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
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};
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void __init arch_init_irq(void)
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{
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/*
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* Clear all of the interrupts while we change the able around a bit.
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* int-handler is not on bootstrap
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*/
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clear_c0_status(ST0_IM);
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/* Sets the first-level interrupt dispatcher. */
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set_except_vector(0, jaguar_handle_int);
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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/* set up the cascading interrupts */
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setup_irq(8, &cascade_mv64340);
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mv64340_irq_init(16);
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set_c0_status(ST0_IM);
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}
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