701 lines
20 KiB
C
701 lines
20 KiB
C
/*
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* ARMv6 Performance counter handling code.
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*
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
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*
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* ARMv6 has 2 configurable performance counters and a single cycle counter.
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* They all share a single reset bit but can be written to zero so we can use
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* that for a reset.
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*
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* The counters can't be individually enabled or disabled so when we remove
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* one event and replace it with another we could get spurious counts from the
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* wrong event. However, we can take advantage of the fact that the
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* performance counters can export events to the event bus, and the event bus
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* itself can be monitored. This requires that we *don't* export the events to
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* the event bus. The procedure for disabling a configurable counter is:
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* - change the counter to count the ETMEXTOUT[0] signal (0x20). This
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* effectively stops the counter from counting.
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* - disable the counter's interrupt generation (each counter has it's
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* own interrupt enable bit).
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* Once stopped, the counter value can be written as 0 to reset.
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*
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* To enable a counter:
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* - enable the counter's interrupt generation.
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* - set the new event type.
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*
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* Note: the dedicated cycle counter only counts cycles and can't be
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* enabled/disabled independently of the others. When we want to disable the
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* cycle counter, we have to just disable the interrupt reporting and start
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* ignoring that counter. When re-enabling, we have to reset the value and
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* enable the interrupt.
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*/
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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enum armv6_perf_types {
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ARMV6_PERFCTR_ICACHE_MISS = 0x0,
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ARMV6_PERFCTR_IBUF_STALL = 0x1,
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ARMV6_PERFCTR_DDEP_STALL = 0x2,
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ARMV6_PERFCTR_ITLB_MISS = 0x3,
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ARMV6_PERFCTR_DTLB_MISS = 0x4,
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ARMV6_PERFCTR_BR_EXEC = 0x5,
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ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
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ARMV6_PERFCTR_INSTR_EXEC = 0x7,
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ARMV6_PERFCTR_DCACHE_HIT = 0x9,
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ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
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ARMV6_PERFCTR_DCACHE_MISS = 0xB,
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ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
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ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
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ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
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ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
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ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
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ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
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ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
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ARMV6_PERFCTR_NOP = 0x20,
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};
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enum armv6_counters {
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ARMV6_CYCLE_COUNTER = 1,
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ARMV6_COUNTER0,
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ARMV6_COUNTER1,
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};
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/*
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* The hardware events that we support. We do support cache operations but
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* we have harvard caches and no way to combine instruction and data
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* accesses/misses in hardware.
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*/
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static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
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[PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
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[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
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};
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static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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/*
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* The performance counters don't differentiate between read
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* and write accesses/misses so this isn't strictly correct,
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* but it's the best we can do. Writes and reads get
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* combined.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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/*
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* The ARM performance counters can count micro DTLB misses,
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* micro ITLB misses and main TLB misses. There isn't an event
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* for TLB misses, so use the micro misses here and if users
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* want the main TLB misses they can use a raw counter.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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enum armv6mpcore_perf_types {
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ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
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ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
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ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
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ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
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ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
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ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
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ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
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ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
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ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
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ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
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ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
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ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
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ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
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ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
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ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
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ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
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ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
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ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
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ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
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ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
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};
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/*
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* The hardware events that we support. We do support cache operations but
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* we have harvard caches and no way to combine instruction and data
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* accesses/misses in hardware.
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*/
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static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
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[PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
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[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
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};
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static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] =
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ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
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[C(RESULT_MISS)] =
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ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] =
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ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
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[C(RESULT_MISS)] =
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ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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/*
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* The ARM performance counters can count micro DTLB misses,
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* micro ITLB misses and main TLB misses. There isn't an event
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* for TLB misses, so use the micro misses here and if users
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* want the main TLB misses they can use a raw counter.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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static inline unsigned long
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armv6_pmcr_read(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
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return val;
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}
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static inline void
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armv6_pmcr_write(unsigned long val)
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{
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asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
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}
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#define ARMV6_PMCR_ENABLE (1 << 0)
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#define ARMV6_PMCR_CTR01_RESET (1 << 1)
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#define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
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#define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
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#define ARMV6_PMCR_COUNT0_IEN (1 << 4)
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#define ARMV6_PMCR_COUNT1_IEN (1 << 5)
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#define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
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#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
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#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
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#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
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#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
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#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
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#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
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#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
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#define ARMV6_PMCR_OVERFLOWED_MASK \
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(ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
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ARMV6_PMCR_CCOUNT_OVERFLOW)
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static inline int
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armv6_pmcr_has_overflowed(unsigned long pmcr)
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{
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return pmcr & ARMV6_PMCR_OVERFLOWED_MASK;
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}
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static inline int
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armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
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enum armv6_counters counter)
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{
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int ret = 0;
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if (ARMV6_CYCLE_COUNTER == counter)
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ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
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else if (ARMV6_COUNTER0 == counter)
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ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
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else if (ARMV6_COUNTER1 == counter)
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ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
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else
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WARN_ONCE(1, "invalid counter number (%d)\n", counter);
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return ret;
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}
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static inline u32
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armv6pmu_read_counter(int counter)
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{
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unsigned long value = 0;
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if (ARMV6_CYCLE_COUNTER == counter)
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asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
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else if (ARMV6_COUNTER0 == counter)
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asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
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else if (ARMV6_COUNTER1 == counter)
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asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
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else
|
|
WARN_ONCE(1, "invalid counter number (%d)\n", counter);
|
|
|
|
return value;
|
|
}
|
|
|
|
static inline void
|
|
armv6pmu_write_counter(int counter,
|
|
u32 value)
|
|
{
|
|
if (ARMV6_CYCLE_COUNTER == counter)
|
|
asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
|
|
else if (ARMV6_COUNTER0 == counter)
|
|
asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
|
|
else if (ARMV6_COUNTER1 == counter)
|
|
asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
|
|
else
|
|
WARN_ONCE(1, "invalid counter number (%d)\n", counter);
|
|
}
|
|
|
|
static void
|
|
armv6pmu_enable_event(struct hw_perf_event *hwc,
|
|
int idx)
|
|
{
|
|
unsigned long val, mask, evt, flags;
|
|
|
|
if (ARMV6_CYCLE_COUNTER == idx) {
|
|
mask = 0;
|
|
evt = ARMV6_PMCR_CCOUNT_IEN;
|
|
} else if (ARMV6_COUNTER0 == idx) {
|
|
mask = ARMV6_PMCR_EVT_COUNT0_MASK;
|
|
evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
|
|
ARMV6_PMCR_COUNT0_IEN;
|
|
} else if (ARMV6_COUNTER1 == idx) {
|
|
mask = ARMV6_PMCR_EVT_COUNT1_MASK;
|
|
evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
|
|
ARMV6_PMCR_COUNT1_IEN;
|
|
} else {
|
|
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Mask out the current event and set the counter to count the event
|
|
* that we're interested in.
|
|
*/
|
|
raw_spin_lock_irqsave(&pmu_lock, flags);
|
|
val = armv6_pmcr_read();
|
|
val &= ~mask;
|
|
val |= evt;
|
|
armv6_pmcr_write(val);
|
|
raw_spin_unlock_irqrestore(&pmu_lock, flags);
|
|
}
|
|
|
|
static irqreturn_t
|
|
armv6pmu_handle_irq(int irq_num,
|
|
void *dev)
|
|
{
|
|
unsigned long pmcr = armv6_pmcr_read();
|
|
struct perf_sample_data data;
|
|
struct cpu_hw_events *cpuc;
|
|
struct pt_regs *regs;
|
|
int idx;
|
|
|
|
if (!armv6_pmcr_has_overflowed(pmcr))
|
|
return IRQ_NONE;
|
|
|
|
regs = get_irq_regs();
|
|
|
|
/*
|
|
* The interrupts are cleared by writing the overflow flags back to
|
|
* the control register. All of the other bits don't have any effect
|
|
* if they are rewritten, so write the whole value back.
|
|
*/
|
|
armv6_pmcr_write(pmcr);
|
|
|
|
perf_sample_data_init(&data, 0);
|
|
|
|
cpuc = &__get_cpu_var(cpu_hw_events);
|
|
for (idx = 0; idx <= armpmu->num_events; ++idx) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
struct hw_perf_event *hwc;
|
|
|
|
if (!test_bit(idx, cpuc->active_mask))
|
|
continue;
|
|
|
|
/*
|
|
* We have a single interrupt for all counters. Check that
|
|
* each counter has overflowed before we process it.
|
|
*/
|
|
if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
|
|
continue;
|
|
|
|
hwc = &event->hw;
|
|
armpmu_event_update(event, hwc, idx, 1);
|
|
data.period = event->hw.last_period;
|
|
if (!armpmu_event_set_period(event, hwc, idx))
|
|
continue;
|
|
|
|
if (perf_event_overflow(event, &data, regs))
|
|
armpmu->disable(hwc, idx);
|
|
}
|
|
|
|
/*
|
|
* Handle the pending perf events.
|
|
*
|
|
* Note: this call *must* be run with interrupts disabled. For
|
|
* platforms that can have the PMU interrupts raised as an NMI, this
|
|
* will not work.
|
|
*/
|
|
irq_work_run();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void
|
|
armv6pmu_start(void)
|
|
{
|
|
unsigned long flags, val;
|
|
|
|
raw_spin_lock_irqsave(&pmu_lock, flags);
|
|
val = armv6_pmcr_read();
|
|
val |= ARMV6_PMCR_ENABLE;
|
|
armv6_pmcr_write(val);
|
|
raw_spin_unlock_irqrestore(&pmu_lock, flags);
|
|
}
|
|
|
|
static void
|
|
armv6pmu_stop(void)
|
|
{
|
|
unsigned long flags, val;
|
|
|
|
raw_spin_lock_irqsave(&pmu_lock, flags);
|
|
val = armv6_pmcr_read();
|
|
val &= ~ARMV6_PMCR_ENABLE;
|
|
armv6_pmcr_write(val);
|
|
raw_spin_unlock_irqrestore(&pmu_lock, flags);
|
|
}
|
|
|
|
static int
|
|
armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
|
|
struct hw_perf_event *event)
|
|
{
|
|
/* Always place a cycle counter into the cycle counter. */
|
|
if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
|
|
if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
|
|
return -EAGAIN;
|
|
|
|
return ARMV6_CYCLE_COUNTER;
|
|
} else {
|
|
/*
|
|
* For anything other than a cycle counter, try and use
|
|
* counter0 and counter1.
|
|
*/
|
|
if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask))
|
|
return ARMV6_COUNTER1;
|
|
|
|
if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask))
|
|
return ARMV6_COUNTER0;
|
|
|
|
/* The counters are all in use. */
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
static void
|
|
armv6pmu_disable_event(struct hw_perf_event *hwc,
|
|
int idx)
|
|
{
|
|
unsigned long val, mask, evt, flags;
|
|
|
|
if (ARMV6_CYCLE_COUNTER == idx) {
|
|
mask = ARMV6_PMCR_CCOUNT_IEN;
|
|
evt = 0;
|
|
} else if (ARMV6_COUNTER0 == idx) {
|
|
mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
|
|
evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
|
|
} else if (ARMV6_COUNTER1 == idx) {
|
|
mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
|
|
evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
|
|
} else {
|
|
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Mask out the current event and set the counter to count the number
|
|
* of ETM bus signal assertion cycles. The external reporting should
|
|
* be disabled and so this should never increment.
|
|
*/
|
|
raw_spin_lock_irqsave(&pmu_lock, flags);
|
|
val = armv6_pmcr_read();
|
|
val &= ~mask;
|
|
val |= evt;
|
|
armv6_pmcr_write(val);
|
|
raw_spin_unlock_irqrestore(&pmu_lock, flags);
|
|
}
|
|
|
|
static void
|
|
armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
|
|
int idx)
|
|
{
|
|
unsigned long val, mask, flags, evt = 0;
|
|
|
|
if (ARMV6_CYCLE_COUNTER == idx) {
|
|
mask = ARMV6_PMCR_CCOUNT_IEN;
|
|
} else if (ARMV6_COUNTER0 == idx) {
|
|
mask = ARMV6_PMCR_COUNT0_IEN;
|
|
} else if (ARMV6_COUNTER1 == idx) {
|
|
mask = ARMV6_PMCR_COUNT1_IEN;
|
|
} else {
|
|
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Unlike UP ARMv6, we don't have a way of stopping the counters. We
|
|
* simply disable the interrupt reporting.
|
|
*/
|
|
raw_spin_lock_irqsave(&pmu_lock, flags);
|
|
val = armv6_pmcr_read();
|
|
val &= ~mask;
|
|
val |= evt;
|
|
armv6_pmcr_write(val);
|
|
raw_spin_unlock_irqrestore(&pmu_lock, flags);
|
|
}
|
|
|
|
static const struct arm_pmu armv6pmu = {
|
|
.id = ARM_PERF_PMU_ID_V6,
|
|
.name = "v6",
|
|
.handle_irq = armv6pmu_handle_irq,
|
|
.enable = armv6pmu_enable_event,
|
|
.disable = armv6pmu_disable_event,
|
|
.read_counter = armv6pmu_read_counter,
|
|
.write_counter = armv6pmu_write_counter,
|
|
.get_event_idx = armv6pmu_get_event_idx,
|
|
.start = armv6pmu_start,
|
|
.stop = armv6pmu_stop,
|
|
.cache_map = &armv6_perf_cache_map,
|
|
.event_map = &armv6_perf_map,
|
|
.raw_event_mask = 0xFF,
|
|
.num_events = 3,
|
|
.max_period = (1LLU << 32) - 1,
|
|
};
|
|
|
|
static const struct arm_pmu *__init armv6pmu_init(void)
|
|
{
|
|
return &armv6pmu;
|
|
}
|
|
|
|
/*
|
|
* ARMv6mpcore is almost identical to single core ARMv6 with the exception
|
|
* that some of the events have different enumerations and that there is no
|
|
* *hack* to stop the programmable counters. To stop the counters we simply
|
|
* disable the interrupt reporting and update the event. When unthrottling we
|
|
* reset the period and enable the interrupt reporting.
|
|
*/
|
|
static const struct arm_pmu armv6mpcore_pmu = {
|
|
.id = ARM_PERF_PMU_ID_V6MP,
|
|
.name = "v6mpcore",
|
|
.handle_irq = armv6pmu_handle_irq,
|
|
.enable = armv6pmu_enable_event,
|
|
.disable = armv6mpcore_pmu_disable_event,
|
|
.read_counter = armv6pmu_read_counter,
|
|
.write_counter = armv6pmu_write_counter,
|
|
.get_event_idx = armv6pmu_get_event_idx,
|
|
.start = armv6pmu_start,
|
|
.stop = armv6pmu_stop,
|
|
.cache_map = &armv6mpcore_perf_cache_map,
|
|
.event_map = &armv6mpcore_perf_map,
|
|
.raw_event_mask = 0xFF,
|
|
.num_events = 3,
|
|
.max_period = (1LLU << 32) - 1,
|
|
};
|
|
|
|
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
|
|
{
|
|
return &armv6mpcore_pmu;
|
|
}
|
|
#else
|
|
static const struct arm_pmu *__init armv6pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
|