184 lines
4.2 KiB
C
184 lines
4.2 KiB
C
/*
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* arch/arm/mach-orion5x/wnr854t-setup.c
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ethtool.h>
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#include <net/dsa.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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static unsigned int wnr854t_mpp_modes[] __initdata = {
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MPP0_GPIO, /* Power LED green (0=on) */
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MPP1_GPIO, /* Reset Button (0=off) */
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MPP2_GPIO, /* Power LED blink (0=off) */
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MPP3_GPIO, /* WAN Status LED amber (0=off) */
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MPP4_GPIO, /* PCI int */
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MPP5_GPIO, /* ??? */
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MPP6_GPIO, /* ??? */
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MPP7_GPIO, /* ??? */
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MPP8_UNUSED, /* ??? */
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MPP9_GIGE, /* GE_RXERR */
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MPP10_UNUSED, /* ??? */
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MPP11_UNUSED, /* ??? */
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MPP12_GIGE, /* GE_TXD[4] */
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MPP13_GIGE, /* GE_TXD[5] */
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MPP14_GIGE, /* GE_TXD[6] */
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MPP15_GIGE, /* GE_TXD[7] */
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MPP16_GIGE, /* GE_RXD[4] */
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MPP17_GIGE, /* GE_RXD[5] */
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MPP18_GIGE, /* GE_RXD[6] */
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MPP19_GIGE, /* GE_RXD[7] */
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0,
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};
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/*
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* 8M NOR flash Device bus boot chip select
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*/
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#define WNR854T_NOR_BOOT_BASE 0xf4000000
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#define WNR854T_NOR_BOOT_SIZE SZ_8M
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static struct mtd_partition wnr854t_nor_flash_partitions[] = {
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{
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.name = "kernel",
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.offset = 0x00000000,
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.size = 0x00100000,
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}, {
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.name = "rootfs",
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.offset = 0x00100000,
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.size = 0x00660000,
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}, {
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.name = "uboot",
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.offset = 0x00760000,
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.size = 0x00040000,
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},
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};
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static struct physmap_flash_data wnr854t_nor_flash_data = {
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.width = 2,
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.parts = wnr854t_nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
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};
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static struct resource wnr854t_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = WNR854T_NOR_BOOT_BASE,
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.end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device wnr854t_nor_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &wnr854t_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &wnr854t_nor_flash_resource,
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};
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static struct mv643xx_eth_platform_data wnr854t_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct dsa_chip_data wnr854t_switch_chip_data = {
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.port_names[0] = "lan3",
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.port_names[1] = "lan4",
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.port_names[2] = "wan",
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.port_names[3] = "cpu",
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.port_names[5] = "lan1",
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.port_names[7] = "lan2",
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};
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static struct dsa_platform_data wnr854t_switch_plat_data = {
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.nr_chips = 1,
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.chip = &wnr854t_switch_chip_data,
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};
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static void __init wnr854t_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(wnr854t_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_eth_init(&wnr854t_eth_data);
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orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
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orion5x_uart0_init();
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orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
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WNR854T_NOR_BOOT_SIZE);
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platform_device_register(&wnr854t_nor_flash);
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}
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static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
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u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* Mini-PCI slot.
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*/
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if (slot == 7)
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return gpio_to_irq(4);
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return -1;
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}
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static struct hw_pci wnr854t_pci __initdata = {
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.nr_controllers = 2,
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.swizzle = pci_std_swizzle,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = wnr854t_pci_map_irq,
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};
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static int __init wnr854t_pci_init(void)
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{
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if (machine_is_wnr854t())
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pci_common_init(&wnr854t_pci);
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return 0;
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}
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subsys_initcall(wnr854t_pci_init);
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MACHINE_START(WNR854T, "Netgear WNR854T")
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/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
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.boot_params = 0x00000100,
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.init_machine = wnr854t_init,
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.map_io = orion5x_map_io,
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.init_early = orion5x_init_early,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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.fixup = tag_fixup_mem32,
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MACHINE_END
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